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70T3799MS133BBG8 Datasheet(PDF) 11 Page - Integrated Device Technology |
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70T3799MS133BBG8 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 25 page 6.42 IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges 11 An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/W ADDRESS CE0 CLK CE1 BEn (3) DATAOUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 5687 drw 05 (1) (1) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (4) (1 Latency) (5) (5) , Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE'X' = VIH)(1,2) NOTES: 1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge. 2. ADS = VIL, CNTEN and REPEAT = VIH. 3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 6. "x" denotes Left or Right port. The diagram is with respect to that port. Timing Waveform of Read Cycle for Flow-through Output (FT/PIPE"X" = VIL)(1,2,6) An An + 1 An + 2 An + 3 tCYC1 tCH1 tCL1 R/W ADDRESS DATAOUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 5687 drw 06 (5) (1) CE1 BEn (3) tSB tHB tSW tHW tSA tHA tDC tDC (4) tSC tHC tSB tHB , |
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