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70V3379S6BFG8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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70V3379S6BFG8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 17 page ©2015 Integrated Device Technology, Inc. AUGUST 2015 DSC 4833/13 1 HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE CNTRSTR Counter/ Address Reg. A14R A0R Counter/ Address Reg. CNTENR ADSR CNTENL ADSL CNTRSTL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R B W 0 L B W 1 L B W 1 R B W 0 R I/O0L -I/O17 L I/O0R -I/O17R Din_L ADDR_L Din_R ADDR_R OER OEL 4833 tbl 01 UBL LBL R/ WL CE0L UBR LBR R/ WR CE0R CE1R CE1L 32K x 18 MEMORY ARRAY CLKR CLKL ., A14L A0L Functional Block Diagram Features: ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 4.2/5/6ns (max.) – Industrial: 5ns (max) ◆ Pipelined output mode ◆ Counter enable and reset features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Full synchronous operation on both ports – 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) – Fast 4.2ns clock to data out – 1.8ns setup to clock and 0.7ns hold on all control, data, and address inputs @ 133MHz – Data input, address, byte enable and control registers – Self-timedwriteallowsfastcycletime ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ LVTTL- compatible, single 3.3V (±150mV) power supply for core ◆ LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV) power supply for I/Os and control signals on each port ◆ Industrial temperature range (-40°C to +85°C) is available for selected speeds ◆ Available in a 128-pin Thin Quad Plastic Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid Array IDT70V3379S ◆ Green parts available, see ordering information |
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