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IDT70914S Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT70914S Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 12 page 6.42 7 Comm IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C) NOTES: 1. Transition is measured 0mV from Low or High impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. Industrial temperature: for specific speeds, packages and powers contact your sales office. 70914S12 Com'l Only 70914S15 Com'l Only Symbol Parameter Min.Max.Min.Max. Unit tCYC Clock Cycle Time 16 ____ 20 ____ ns tCH Clock High Time 6 ____ 6 ____ ns tCL Clock Low Time 6 ____ 6 ____ ns tCD Clock High to Output Valid ____ 12 ____ 15 ns tS Registered Signal Set-up Time 4 ____ 4 ____ ns tH Registered Signal Hold Time 1 ____ 1 ____ ns tDC Data Output Hold After Clock High 3 ____ 3 ____ ns tCKLZ Clock High to Output Low-Z(1,2) 2 ____ 2 ____ ns tCKHZ Clock High to Output High-Z(1,2) ____ 7 ____ 7ns tOE Output Enable to Output Valid ____ 7 ____ 8ns tOLZ Output Enable to Output Low-Z(1,2) 0 ____ 0 ____ ns tOHZ Output Disable to Output High-Z(1,2) ____ 7 ____ 7ns tSCK Clock Enable, Disable Set-up Time 4 ____ 4 ____ ns tHCK Clock Enable, Disable Hold Time 2 ____ 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 25 ____ 30 ns tCSS Clock-to-Clock Setup Time ____ 13 ____ 15 ns 3490 tbl 08a 70914S20 Com'l Only Symbol Parameter Min. Max. Unit tCYC Clock Cycle Time 20 ____ ns tCH Clock High Time 8 ____ ns tCL Clock Low Time 8 ____ ns tCD Clock High to Output Valid ____ 20 ns tS Registered Signal Set-up Time 5 ____ ns tH Registered Signal Hold Time 1 ____ ns tDC Data Output Hold After Clock High 3 ____ ns tCKLZ Clock High to Output Low-Z(1,2) 2 ____ ns tCKHZ Clock High to Output High-Z(1,2) ____ 9ns tOE Output Enable to Output Valid ____ 10 ns tOLZ Output Enable to Output Low-Z(1,2) 0 ____ ns tOHZ Output Disable to Output High-Z(1,2) ____ 9ns tSCK Clock Enable, Disable Set-up Time 5 ____ ns tHCK Clock Enable, Disable Hold Time 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 35 ns tCSS Clock-to-Clock Setup Time ____ 15 ns 3490 tbl 08b |
Similar Part No. - IDT70914S_16 |
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Similar Description - IDT70914S_16 |
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