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70V9359L9PFGI Datasheet(PDF) 4 Page - Integrated Device Technology |
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70V9359L9PFGI Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 17 page 6.42 IDT70V9359/49L High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges 4 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Truth Table I—Read/Write and Enable Control(1,2,3) Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (3) R/ WL R/ WR Read/Write Enable OEL OER Output Enable A0L - A12L (1) A0R - A12R (1) Address I/O0L - I/O17L I/O0R - I/O17R Data Input/Output CLKL CLKR Clock UBL UBR Upper Byte Select(2) LBL LBR Lower Byte Select(2) ADSL ADSR Address Strobe Enable CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through / Pipeline VDD Power (3.3V) VSS Ground (0V) 5638 tbl 01 OE CLK CE0(5) CE1 (5) UB(4) LB(4) R/ W Upper Byte I/O9-17 Lower Byte I/O0-8 MODE X ↑ H X X X X High-Z High-Z Deselected–Power Down X ↑ X L X X X High-Z High-Z Deselected–Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ LH LH L DATAIN High-Z Write to Upper Byte Only X ↑ LH H L L High-Z DATAIN Write to Lower Byte Only X ↑ L H LLL DATAIN DATAIN Write to Both Bytes L ↑ LH LH H DATAOUT High-Z Read Upper Byte Only L ↑ LH H L H High-Z DATAOUT Read Lower Byte Only L ↑ LH L L H DATAOUT DATAOUT Read Both Bytes H X L H X X X High-Z High-Z Outputs Disabled 5638 tbl 02 NOTE: 1. A12 is a NC for IDT70V9349. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE1 are single buffered when FT/PIPE = VIL, CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. 4 LB and UB are single buffered regardless of state of FT/PIPE. 5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. |
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