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70V9199L12PFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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70V9199L12PFG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 17 page ©2010 Integrated Device Technology, Inc. JULY 2010 DSC-4859/7 1 Functional Block Diagram Features: ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 9/12ns (max.) – Industrial: 9ns (max.) ◆ Low-power operation – IDT70V9199/099L Active: 500mW (typ.) Standby: 1.5mW (typ.) ◆ Flow-Through or Pipelined output mode on either port via the FT/PIPE pins ◆ Dual chip enables allow for depth expansion without additional logic ◆ Counter enable and reset features ◆ Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 9 ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 66 MHz operation in Pipelined output mode ◆ LVTTL- compatible, single 3.3V (±0.3V) power supply ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Available in a 100-pin Thin Quad Flatpack (TQFP) ◆ Green parts available, see ordering information IDT70V9199/099L 0 1 0/1 1 0/1 0 R/ WR OER CE0R CE1R FT/PIPER I/O Control MEMORY ARRAY Counter/ Address Reg. I/O Control 4859 drw 01 A16R A0R CLKR ADSR CNTENR CNTRSTR A0L CLKL ADSL A16L CNTENL CNTRSTL Counter/ Address Reg. R/ WL CE0L OEL CE1L I/O0L - I/O8L(1) I/O0R -I/O8R(1) . 1 0/1 0 0 1 0/1 FT/PIPEL HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM NOTE: 1. I/O0X - I/O7X for IDT70V9099. |
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