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70V3599S166BFG Datasheet(PDF) 6 Page - Integrated Device Technology |
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70V3599S166BFG Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 23 page  6.42 6 High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges IDT70V3599/89S NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = X. 3. OE is an asynchronous input signal. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. Truth Table I—Read/Write and Enable Control(1,2,3,4) OE CLK CE0 CE1 BE3 BE2 BE1 BE0 R/W Byte 3 I/O27-35 Byte 2 I/O18-26 Byte 1 I/O9-17 Byte 0 I/O0-8 MODE X ↑ H X XXXXX High-Z High-Z High-Z High-Z Deselected–Power Down X ↑ X L XXXXX High-Z High-Z High-Z High-Z Deselected–Power Down X ↑ L H H H H H X High-Z High-Z High-Z High-Z All Bytes Deselected X ↑ L H H H H L L High-Z High-Z High-Z DIN Write to Byte 0 Only X ↑ LH H H LH L High-Z High-Z DIN High-Z Write to Byte 1 Only X ↑ LH H L H H L High-Z DIN High-Z High-Z Write to Byte 2 Only X ↑ LH LH H H L DIN High-Z High-Z High-Z Write to Byte 3 Only X ↑ L H H H L L L High-Z High-Z DIN DIN Write to Lower 2 Bytes Only X ↑ LH L L H H L DIN DIN High-Z High-Z Write to Upper 2 bytes Only X ↑ L H LLLLL DIN DIN DIN DIN Write to All Bytes L ↑ L H H H H L H High-Z High-Z High-Z DOUT Read Byte 0 Only L ↑ LH H H LH H High-Z High-Z DOUT High-Z Read Byte 1 Only L ↑ LH H L H H H High-Z DOUT High-Z High-Z Read Byte 2 Only L ↑ LH LH H H H DOUT High-Z High-Z High-Z Read Byte 3 Only L ↑ LH H H L L H High-Z High-Z DOUT DOUT Read Lower 2 Bytes Only L ↑ LH L L H H H DOUT DOUT High-Z High-Z Read Upper 2 Bytes Only L ↑ L H LLLL H DOUT DOUT DOUT DOUT Read All Bytes H ↑ L H LLLL X High-Z High-Z High-Z High-Z Outputs Disabled 5617 tbl 02 Truth Table II—Address Counter Control(1,2) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. External Address Previous Internal Address Internal Address Used CLK ADS CNTEN REPEAT(6) I/O(3) MODE XX An ↑ XX L(4) DI/O(0) Counter Reset to last valid ADS load An X An ↑ L(4) XH DI/O (n) External Address Used An Ap Ap ↑ HH H DI/O(p) External Address Blocked—Counter disabled (Ap reused) XAp Ap + 1 ↑ H L(5) HDI/O(p+1) Counter Enabled—Internal Address generation 5617 tbl 03 |
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