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70V7339S200BCGI Datasheet(PDF) 11 Page - Integrated Device Technology |
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70V7339S200BCGI Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 22 page 6.42 IDT70V7339S High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges 11 An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/W ADDRESS CE0 CLK CE1 UB/LB (3) DATAOUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 5628 drw 06 (1) (1) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (4) (1 Latency) (5) (5) Timing Waveform of Read Cycle for Pipelined Operation (ADS Operation) (FT/PIPE'X' = VIH)(2) NOTES: 1. OEisasynchronouslycontrolled;allotherinputsaresynchronoustotherisingclockedge. 2. ADS = VIL, CNTEN and REPEAT = VIH. 3. Theoutputisdisabled(High-Impedancestate)byCE0=VIH,CE1=VIL,UB/LB=VIHfollowingthenextrisingedgeoftheclock.Referto TruthTable1. 4. AddressesdonothavetobeaccessedsequentiallysinceADS=VILconstantlyloadstheaddressontherisingedgeoftheCLK;numbers areforreferenceuseonly. 5. IfUB/LBwasHIGH,thentheappropriateByteofDATAOUTforQn+2wouldbedisabled(High-Impedancestate). 6. "x"denotesLeftorRightport.Thediagramiswithrespecttothatport. Timing Waveform of Read Cycle for Flow-through Output (FT/PIPE"X" = VIL)(2,6) An An + 1 An + 2 An + 3 tCYC1 tCH1 tCL1 R/W ADDRESS DATAOUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 5628 drw 07 (5) (1) CE1 BEn (3) tSB tHB tSW tHW tSA tHA tDC tDC (4) tSC tHC tSB tHB (5) |
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