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70V9369L7PFG Datasheet(PDF) 11 Page - Integrated Device Technology

Part # 70V9369L7PFG
Description  HIGH-SPEED 3.3V 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

70V9369L7PFG Datasheet(HTML) 11 Page - Integrated Device Technology

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6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
R/W
ADDRESS
An
An +1
An + 2
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
5648 drw 11
Qn
Qn + 3
DATAOUT
CE1
UB, LB
tCD2
tCKHZ
tCKLZ
tCD2
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
tCH2
tCL2
tCYC2
READ
NOP
READ
tSD tHD
(4)
(2)
(1)
(1)
tSW tHW
WRITE
(5)
.
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
DATAIN
Dn + 3
Dn + 2
CE0
CLK
5648 drw 12
DATAOUT
Qn
Qn + 4
CE1
UB, LB
OE
tCH2
tCL2
tCYC2
tCKLZ(1)
tCD2
tOHZ(1)
tCD2
tSD tHD
READ
WRITE
READ
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
(4)
(2)
tSW tHW
.
NOTES:
1. Transitionismeasured0mVfromLoworHigh-impedancevoltagewith theOutputTestLoad(Figure2).
2. Outputstate(High,Low,orHigh-impedance)isdeterminedbythepreviouscyclecontrolsignals.
3. CE0, UB, LB,andADS = VIL; CE1 andCNTRST = VIH. "NOP" is "No Operation".
4. AddressesdonothavetobeaccessedsequentiallysinceADS=VILconstantlyloadstheaddressontherisingedgeoftheCLK;numbersarefor
referenceuseonly.
5. "NOP"is"NoOperation."Datainmemoryattheselectedaddressmaybecorruptedandshouldbere-writtentoguaranteedataintegrity.


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