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70V9289L9PRFGI8 Datasheet(PDF) 8 Page - Integrated Device Technology |
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70V9289L9PRFGI8 Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 19 page  6.42 8 IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V) DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V) NOTE: 1. At VDD < 2.0V input leakages are undefined. NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. Symbol Parameter Test Conditions 70V9389/289L Unit Min. Max. |ILI| Input Leakage Current(1) VDD = 3.6V, VIN = 0V to VDD ___ 5µA |ILO| Output Leakage Current CE = VIH or CE1 = VIL, VOUT = 0V to VDD ___ 5µA VOL Output Low Voltage IOL = +4mA ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ V 4856 tbl 08 70V9389/289L7 Com'l Only 70V9389/289L9 Com'l & Ind 70V9389/289L12 Com'l Only Symbol Parameter Test Condition Version Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit IDD Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) COM'L L 200 250 175 230 150 200 mA IND L ____ ____ 180 240 ____ ____ ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH f = fMAX(1) COM'L L 50 75 40 65 30 50 mA IND L ____ ____ 50 70 ____ ____ ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) COM'L L 130 165 110 145 95 130 mA IND L ____ ____ 110 155 ____ ____ ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) COM'L L 0.420.4 20.4 2 mA IND L ____ ____ 0.4 2 ____ ____ ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) COM'L L 130 160 100 140 90 125 mA IND L ____ ____ 100 155 ____ ____ 4856 tbl 09a |
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