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70V9289L7PFG8 Datasheet(PDF) 2 Page - Integrated Device Technology |
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70V9289L7PFG8 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 19 page 6.42 2 IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 70 69 68 67 66 65 91 71 NC NC NC NC A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR VSS VDD NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC NC NC I/O12L I/O11L VDD NC I/O10L I/O9L I/O8L VDD I/O7L I/O6L I/O5L I/O4L VSS I/O3L I/O2L VSS I/O1L I/O0L VDD VSS I/O0R I/O2R I/O1R VSS I/O4R I/O5R I/O6R VDD I/O7R I/O8R I/O9R I/O10R NC VSS I/O11R I/O12R VDD I/O3R 70V9389PRF PK128(4) 128-Pin TQFP Top View(5) 4856 drw 02 CNTENL CLKL ADSL 02/25/14 Description: The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memorycellstoallowsimultaneousaccessofanyaddressfrombothports. Registersoncontrol,data,andaddressinputsprovideminimalsetupand holdtimes.Thetiminglatitudeprovidedbythisapproachallowssystems to be designed with very short cycle times. Pin Configuration(1,2,3) NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground. 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. With an input data register, the IDT70V9389/289 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 500mW of power. |
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