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70V9079L6PFGI8 Datasheet(PDF) 3 Page - Integrated Device Technology |
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70V9079L6PFGI8 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 19 page 6.42 IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 3 Pin Names Truth Table II—Address Counter Control(1,2,3) Truth Table I—Read/Write and Enable Control(1,2,3) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Left Port Right Port Names CE0L , CE1L CE0R , CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A15L(1) A0R - A15R(1) Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output CLKL CLKR Clock ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT /PIPEL FT /PIPER Flow-Through/Pipeline VDD Power (3.3V) VSS Ground (0V) 3750 tbl 01 OE CLK CE0 CE1 R/ W I/O0-7 Mode X ↑ H X X High-Z Deselected - Power Down X ↑ X L X High-Z Deselected - Power Down X ↑ LH L DATAIN Write L ↑ LH H DATAOUT Read H X L H X High-Z Outputs Disabled 3750 tbl 02 External Address Previous Internal Address Internal Address Used CLK ADS CNTEN CNTRST I/O(3) MODE An X An ↑ L(4) XH DI/O (n) External Address Used XAn An + 1 ↑ H L(5) HDI/O(n+1) Counter Enabled—Internal Address generation XAn + 1 An + 1 ↑ HH H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) XX A0 ↑ XX L(4) DI/O(0) Counter Reset to Address 0 3750 tbl 03 NOTE: 1. A15X is a NC for IDT70V9079. NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE1 are single buffered when FT/PIPE = VIL, CE o and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. |
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