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SN74TVC3306 Datasheet(PDF) 5 Page - Texas Instruments |
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SN74TVC3306 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 9 page  www.ti.com APPLICATION INFORMATION 150 Ω Open-Drain CPU Interface Motherboard Interface VREF(1) = 1.5 V GATE(1) B1 (VBIAS)(1) TVC3306 (1) VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS. B3 8 7 6 5 1 2 3 4 150 Ω 200 k Ω B2 VDDREF = 3.3 V VDPU = 2.5 V A3 A2 A1 Application Operating Conditions SN74TVC3306 DUAL VOLTAGE CLAMP SCDS112C – MARCH 2001 – REVISED MARCH 2005 Figure 2. Typical Application Circuit For the clamping configuration, the common GATE input must be connected to one side (An or Bn) of any one of the pass transistors, making that the VBIAS connection of the reference transistor and the opposite side (Bn or An) the VREF connection. When VBIAS is connected through a 200-kΩ resistor to a 3-V to 5.5-V VCC supply and VREF is set to 0 V to VCC – 0.6 V, the output of each switch has a maximum clamp voltage equal to VREF. A filter capacitor on VBIAS is recommended. see Figure 2 MIN TYP(1) MAX UNIT VBIAS BIAS voltage VREF + 0.6 2.1 5 V VGATE GATE voltage VREF + 0.6 2.1 5 V VREF Reference voltage 0 1.5 4.4 V VDPU Drain pullup voltage 2.36 2.5 2.64 V IPASS Pass-transistor current 14 mA IREF Reference-transistor current 5 µA TA Operating free-air temperature –40 85 °C (1) All typical values are at TA = 25°C. 5 |
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