AD9363 datasheet(28/32 Pages) AD

Part #	AD9363

Description	Radio frequency (RF) 2 횞 2 transceiver with integrated 12-bit DACs and ADCs

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AD9363

Data Sheet

Rev. D | Page 28 of 32

THEORY OF OPERATION

GENERAL

The AD9363 is a highly integrated radio frequency (RF)

transceiver capable of being configured for a wide range of

applications. The device integrates all RF, mixed-signal, and

digital blocks necessary to provide all transceiver functions in a

single device. Programmability allows this broadband transceiver

to be adapted for use with multiple communication standards,

including FDD and TDD systems. This programmability also

allows the device to interface to various BBPs using a single 12-

bit parallel data port, dual 12-bit parallel data ports, or a 12-bit

low voltage differential signaling (LVDS) interface.

The AD9363 also provides self calibration and AGC systems to

maintain a high performance level under varying temperatures

and input signal conditions. In addition, the device includes

several test modes that allow system designers to insert test tones

and create internal loopback modes to debug their designs

during prototyping and optimize their radio configuration for a

specific application.

RECEIVER

The receiver section contains all blocks necessary to receive RF

signals and convert them to digital data that is usable by a BBP.

Two independently controlled channels can receive signals from

different sources, allowing the device to be used in multiple

input, multiple output (MIMO) systems while sharing a

common frequency synthesizer.

Each channel has three inputs that can be multiplexed to the

signal chain, making the AD9363 suitable for use in diversity

systems with multiple antenna inputs. The receiver is a direct

conversion system that contains a low noise amplifier (LNA)

followed by matched in-phase (I) and quadrature (Q) amplifiers,

mixers, and band shaping filters that downconvert received

signals to baseband for digitization. External LNAs can also

be interfaced to the device, allowing designers the flexibility to

customize the receiver front end for their specific application.

Gain control is achieved by following a preprogrammed gain

index map that distributes gain among the blocks for optimal

performance at each level. This gain control can be achieved by

enabling the internal AGC in either fast or slow mode or by

using manual gain control, allowing the BBP to make the gain

adjustments as needed. Additionally, each channel contains

independent RSSI measurement capability, dc offset tracking,

and all circuitry necessary for self calibration.

The receivers include 12-bit, sigma-delta (Σ-Δ) ADCs and adjust-

able sample rates that produce data streams from the received

signals. The digitized signals can be conditioned further by a

series of decimation filters and a fully programmable 128-tap

FIR filter with additional decimation settings. The sample rate

of each digital filter block can also be adjusted by changing the

decimation factors to produce the desired output data rate.

TRANSMITTER

The transmitter section consists of two identical and indepen-

dently controlled channels that provide all digital processing,

mixed-signal, and RF blocks necessary to implement a direct

conversion system while sharing a common frequency synthe-

sizer. The digital data received from the BBP passes through a

fully programmable 128-tap FIR filter with interpolation options.

The FIR output is sent to a series of interpolation filters that

provide additional filtering and data rate interpolation prior to

reaching the DAC. Each 12-bit DAC has an adjustable sampling

rate. Both the I and Q channels are fed to the RF block for

upconversion.

After being converted to baseband analog signals, the I and Q

signals are filtered to remove sampling artifacts and provide band

shaping, and then they are passed to the upconversion mixers.

At this point, the I and Q signals are recombined and modulated

on the carrier frequency for transmission to the output stage.

The output stage provides attenuation control that provides a

range of output levels while keeping the output impedance at 50 Ω.

A wide range of attenuation adjustment with fine granularity is

included to help designers optimize SNR.

Self calibration circuitry is included in the transmit channel to

provide internal adjustment capability. The transmitter also

provides a Tx monitor block that receives the transmitter output

and routes it back through an unused receiver channel to the

BBP for signal monitoring. The Tx monitor blocks are available

only in TDD mode operation while the receiver is idle.

CLOCK INPUT OPTIONS

The AD9363 uses a reference clock provided by an external

oscillator or clock distribution device (such as the AD9548)

connected to the XTALN pin. The frequency of this reference

clock can vary from 10 MHz to 80 MHz. This reference clock

supplies the synthesizer blocks that generate all data clocks,

sample clocks, and local oscillators inside the device.

SYNTHESIZERS

RF PLLs

The AD9363 contains two identical synthesizers to generate the

required LO signals for the RF signal paths—one for the receiver

and one for the transmitter. PLL synthesizers are fractional N

designs that incorporate completely integrated VCOs and loop

filters. In TDD mode, the synthesizers turn on and off as appropri-

ate for the Rx and Tx frames. In FDD mode, the Tx PLL and the

Rx PLL can be activated at the same time. These PLLs require no

external components.

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