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X25138PI-V Datasheet(PDF) 5 Page - Xicor Inc. |
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X25138PI-V Datasheet(HTML) 5 Page - Xicor Inc. |
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5 / 18 page  X25138 5 Hold Operation The HOLD input should be HIGH (at VIH) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to VCC or tied to VCC through a resistor. Operational Notes The X25138 powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent in- advertent writes: • The “write enable” latch is reset upon power-up. • A WREN instruction must be issued to set the “write enable” latch. •CS must come HIGH at the proper clock count in or- der to start a write cycle. Figure 1. Read E2PROM Array Operation Sequence 012 34567 89 10 20 21 22 23 24 25 26 27 28 29 30 7 65432 10 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 16 BIT ADDRESS 15 14 13 3 2 1 0 7037 FRM F03 Figure 2. Read Status Register Operation Sequence 0123456789 10 11 12 13 14 76543210 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 7037 FRM F04 |
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Similar Description - X25138PI-V |
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