0 Hz/DC to 14 GHz, Single-Pole, Four-Throw

MEMS Switch with Integrated Driver

Data Sheet

ADGM1304

Rev. C

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FEATURES

Fully operational down to 0 Hz/dc

Actuation lifetime: 1 billion cycles (minimum)

−3 dB bandwidth

11 GHz (typical) for RF1, RF4

14 GHz (typical) for RF2, RF3

Insertion loss: 0.26 dB (typical) at 2.5 GHz

Isolation: 24 dB (typical) at 2.5 GHz

High linearity IIP3: 69 dBm (typical)

On switching time: 30 μs (typical)

Radio frequency (RF) power rating: 36 dBm (maximum)

On resistance 1.6 Ω (typical)

Supply voltage: 3.1 V to 3.3 V nominal

Hermetically sealed switch contacts

Integrated driver removes the need for an external driver

CMOS-/LVTTL-compatible

Parallel interface

24-lead, 5 mm × 4 mm × 0.95 mm, LFCSP

APPLICATIONS

Relay replacements

Automatic test equipment (ATE): RF/digital/mixed signals

Load/probe boards: RF/digital/mixed signals

RF test instrumentation

Reconfigurable filters/attenuators

High performance RF switching

GENERAL DESCRIPTION

The ADGM1304 is a wideband, single-pole, four-throw (SP4T)

switch, fabricated using Analog Devices, Inc., microelectro-

mechanical system (MEMS) switch technology. This technology

enables a small, wide bandwidth, highly linear, low insertion

loss switch that is operational down to 0 Hz/dc, making it an

ideal switching solution for a wide range of RF applications.

An integrated control chip generates the high voltage necessary

to electrostatically actuate the switch via a complementary metal-

oxide semiconductor (CMOS)-/low voltage transistor-transistor

logic (LVTTL)-compatible parallel interface. All four switches are

independently controllable.

The ADGM1304 is packaged in a 24-lead, 5 mm × 4 mm ×

0.95 mm, lead frame chip-scale package (LFCSP).

FUNCTIONAL BLOCK DIAGRAM

CHARGE

PUMP

AGND

OSCILLATOR

EXTCLK

REGULATOR

REFERENCE

AND BIAS

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

RF3

RF4

RF1

RF2

ADGM1304

RFC

IN1

IN2

IN3

IN4

SLEEP

NOTES

1. LV = LOW VOLTAGE.

HV = HIGH VOLTAGE.

CLKSEL

RFGND

HV

HV

LV

LV

LV

LV

MUX

÷2

HV

HV

Figure 1.