MOTOROLA CMOS LOGIC DATA

MC14510B

358

Figure 4. Programmable Cascaded Frequency Divider

Note: The programmable frequency divider can be set by applying the desired divide ratio, in BCD, to the preset inputs. For

example, the maximum divide ratio of 99 may be obtained by applying a 10011001 to the preset inputs P0 to P7. For this divide

operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and

should be avoided.

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

PE

Cin

CLOCK

U/D

P1

P2

P3

Cout

L.S.D.

MC14510B

P1

P2

P3

P4

P5

P6

P7

THUMBWHEEL SWITCHES

(OPEN FOR “0”)

RESISTORS = 10 k

Ω

CLOCK (fin)

+ VDD

RESET

OPEN = COUNT

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

M.S.D.

MC14510B

PE

Cin

CLOCK

U/D

R

R

BUFFER

fout

P0

+ VDD

+ VDD

fout =

fin

n

Cout

P4

P1

P2

P3

P4