6

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit)

Commercial and Industrial Temperature Ranges

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

CS

ADDRESS

WE

3101 drw 10

AS

t

t

(5)

DATA VALID

,

NOTES:

1. A write occurs during the overlap of a LOW CS and a LOW WE.

3. During this period, I/O pins are in the output state so that the input signals must not be applied.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

CS

ADDRESS

WE

OE

3101 drw 09

(3)

(6)

(5)

(3)

(5)

DATA VALID

(5)

,