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71V424S15YGI Datasheet(PDF) 5 Page - Integrated Device Technology

Part # 71V424S15YGI
Description  3.3V CMOS Static RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

71V424S15YGI Datasheet(HTML) 5 Page - Integrated Device Technology

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IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
71V424S/L10
71V424S/L12
71V424S/L15
Symbol
Parameter
Min.Max.Min.Max.Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
10
____
12
____
15
____
ns
tAA
Address Access Time
____
10
____
12
____
15
ns
tACS
Chip Select Access Time
____
10
____
12
____
15
ns
tCLZ(1)
Chip Select to Output in Low-Z
4
____
4
____
4
____
ns
tCHZ(1)
Chip Deselect to Output in High-Z
____
5
____
6
____
7ns
tOE
Output Enable to Output Valid
____
5
____
6
____
7ns
tOLZ(1)
Output Enable to Output in Low-Z
0
____
0
____
0
____
ns
tOHZ(1)
Output Disable to Output in High-Z
____
5
____
6
____
7ns
tOH
Output Hold from Address Change
4
____
4
____
4
____
ns
tPU(1)
Chip Select to Power Up Time
0
____
0
____
0
____
ns
tPD(1)
Chip Deselect to Power Down Time
____
10
____
12
____
15
ns
WRITE CYCLE
tWC
Write Cycle Time
10
____
12
____
15
____
ns
tAW
Address Valid to End of Write
8
____
8
____
10
____
ns
tCW
Chip Select to End of Write
8
____
8
____
10
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
8
____
8
____
10
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End of Write
6
____
6
____
7
____
ns
tDH
Data Hold Time
0
____
0
____
0
____
ns
tOW(1)
Output Active from End of Write
3
____
3
____
3
____
ns
tWHZ(1)
Write Enable to Output in High-Z
____
6
____
7
____
7ns
3622 tbl 10
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
AC Electrical Characteristics
(VCC = 3.3V ± 10%, Commercial and Industrial Temperature Ranges)


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