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709379L7PFG8 Datasheet(PDF) 10 Page - Integrated Device Technology |
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709379L7PFG8 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 16 page  6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 10 Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. R/ W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATAIN Dn + 2 CE0 CLK 4845 drw 11 Qn Qn + 3 DATAOUT CE1 UB, LB tCD2 tCKHZ tCKLZ tCD2 tSC tHC tSB tHB tSW tHW tSA tHA tCH2 tCL2 tCYC2 READ NOP READ tSD tHD (4) (2) (1) (1) tSW tHW WRITE (5) R/ W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5 DATAIN Dn + 3 Dn + 2 CE0 CLK 4845 drw 12 DATAOUT Qn Qn + 4 CE1 UB, LB OE tCH2 tCL2 tCYC2 tCKLZ (1) tCD2 tOHZ (1) tCD2 tSD tHD READ WRITE READ tSC tHC tSB tHB tSW tHW tSA tHA (4) (2) tSW tHW |
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