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71V2546XS133BGGI Datasheet(PDF) 1 Page - Integrated Device Technology

Part # 71V2546XS133BGGI
Description  3.3V Synchronous ZBT SRAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

71V2546XS133BGGI Datasheet(HTML) 1 Page - Integrated Device Technology

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APRIL 2011
DSC-5294/07
1
©2011 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.
Features
128K x 36 memory configurations
Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP) and 119 ball grid array (BGA)
IDT71V2546S/XS
128K x 36
3.3V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Pipelined Outputs
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546 contains data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
AClockEnable(CEN)pinallowsoperationoftheIDT71V2546tobe
suspended as long as necessary. All synchronous inputs are ignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Therearethreechipenablepins(CE1,CE2, CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
TheIDT71V2546hasanon-chipburstcounter.Intheburstmode,the
IDT71V2546 can provide four cycles of data for a single address
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBO
inputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
TheIDT71V2546SRAMutilizeIDT's latesthigh-performanceCMOS
process and is packaged in a JEDEC standard 14mm x 20mm 100-pin
thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).
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