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709379L9PFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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709379L9PFG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 16 page ©2015 Integrated Device Technology, Inc. JULY 2015 DSC-4845/7 1 Functional Block Diagram Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial:7.5/9/12ns(max.) – Insustrial: 9ns (max.) ◆ Low-power operation – IDT709379/69L Active: 1.2W (typ.) Standby: 2.5mW (typ.) ◆ Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins ◆ Counter enable and reset features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Full synchronous operation on both ports – 4ns setup to clock and 0ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 10ns cycle time, 100MHz operation in Pipelined output mode ◆ Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility ◆ TTL- compatible, single 5V (±10%) power supply ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Available in a 100-pin Thin Quad Flatpack (TQFP) package ◆ Green parts available, see ordering information HIGH-SPEED 32/16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT709379/69L 0a 1a 0b 1b 0/1 ab I/O Control 1 0/1 0 FT/PIPER R/WR UBR LBR CE0R OER CE1R MEMORY ARRAY Counter/ Address Reg. 4845 drw 01 A14R(1) A0R CLKR ADSR CNTENR CNTRSTR I/O9L-I/O17L I/O0L-I/O8L I/O9R-I/O17R I/O0R-I/O8R A0L CLKL ADSL A14L(1) CNTENL CNTRSTL Counter/ Address Reg. R/WL UBL LBL CE0L OEL CE1L 1 0/1 0 1b 0b 1a 0a 0/1 ba I/O Control FT/PIPEL NOTE: 1. A14X is a NC for IDT709369. |
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