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71V2556XSA100PFG8 Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 71V2556XSA100PFG8
Description  3.3V Synchronous ZBT SRAMs
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

71V2556XSA100PFG8 Datasheet(HTML) 8 Page - Integrated Device Technology

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6.42
6
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
1234567
A
VDDQ
A6
A4
A8
A16
VDDQ
B
NC
CE 2
A3
ADV/LD
A9
CE2
NC
C
A7
A2
VDD
A12
A15
NC
D
I/O16
I/OP3
VSS
NC
VSS
I/OP2
I/O15
E
I/O17
I/O18
VSS
VSS
I/O13
I/O14
F
VDDQ
I/O19
VSS
OE
VSS
I/O12
VDDQ
G
I/O20
I/O21
BW 3
BW 2
I/O11
I/O10
H
I/O22
I/O23
VSS
R/W
VSS
I/O9
I/O8
J
VDDQ
VDD
VDD
VDD
VDDQ
K
I/O24
I/O26
VSS
CLK
VSS
I/O6
I/O7
L
I/O25
I/O27
BW 4
NC
BW 1
I/O4
I/O5
M
VDDQ
I/O28
VSS
CEN
VSS
I/O3
VDDQ
N
I/O29
I/O30
VSS
A1
VSS
I/O2
I/O1
P
I/O31
I/OP4
VSS
A0
VSS
I/O
0
I/O
P1
R
NC
A5
LBO
VDD
A13
T
NC
NC
A10
A11
A14
NC
NC/ZZ(5)
U
VDDQ
NC/TMS(3) NC/TDI(3)
NC/TCK(3) NC/TDO(3) NC/TR ST(3,4)VDDQ
4875 drw 13a
VDD(1)
NC
NC(2)
CE1
NC(2)
VDD(1)
VDD(1)
,
NC
Pin Configuration — 128K x 36, 119 BGA
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is
≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.


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