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IDT71V3558XS200PFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V3558XS200PFG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 25 page JANUARY 2015 DSC-5281/12 1 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. © Pin Description Summary Description TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega- bit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V3556/58 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V3556/58 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected or a write is initiated. Features ◆ ◆ ◆ ◆ ◆ 128K x 36, 256K x 18 memory configurations ◆ ◆ ◆ ◆ ◆ Supports high performance system speed - 200 MHz (x18) (3.2 ns Clock-to-Data Access) ◆ ◆ ◆ ◆ ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ◆ ◆ ◆ ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ ◆ ◆ ◆ ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ ◆ ◆ ◆ ◆ Single R/W (READ/WRITE) control pin ◆ ◆ ◆ ◆ ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ ◆ ◆ ◆ ◆ 4-word burst capability (interleaved or linear) ◆ ◆ ◆ ◆ ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ ◆ ◆ ◆ ◆ Three chip enables for simple depth expansion ◆ ◆ ◆ ◆ ◆ 3.3V power supply (±5%), 3.3V I/O Supply (VDDQ) ◆ ◆ ◆ ◆ ◆ Optional- Boundary Scan JTAG Interface (IEEE 1149.1 compliant) ◆ ◆ ◆ ◆ ◆ Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) A0-A17 Address Inputs Input Synchronous CE1 , CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1 , BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static TMS Test Mode Select Input Synchronous TDI Test Data Input Input Synchronous TCK Test Clock Input N/A TDO Test Data Output Output Synchronous TRST JTAG Reset (Optional) Input Asynchronous ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5281 tbl 01 IDT71V3556S/XS IDT71V3558S/XS IDT71V3556SA/XSA IDT71V3558SA/XSA 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs |
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