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71T75802150PFI8 Datasheet(PDF) 11 Page - Integrated Device Technology |
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71T75802150PFI8 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 23 page 6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 11 Read Operation with Clock Enable Used(1) Write Operation with Clock Enable Used(1) NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Cycle Address R/W ADV/LD CE(2) CEN BW x OE I/O Comments nA0 H L L L X X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 H L L L X X X Clock Valid n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus. n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus. n+5 A2 HL L L X L Q0 Address A0 Read out (bus trans.) n+6 A3 HL L L X L Q1 Address A1 Read out (bus trans.) n+7 A4 HL L L X L Q2 Address A2 Read out (bus trans.) 5313 tbl 17 Cycle Address R/W ADV/LD CE(2) CEN BW x OE I/O Comments nA0 L L L L L X X Address and Control meet setup. n+1 X X X X H X X X Clock n+1 Ignored. n+2 A1 L L LLL X X Clock Valid. n+3 X X X X H X X X Clock Ignored. n+4 X X X X H X X X Clock Ignored. n+5 A2 L L LLL X D0 Write Data D0 n+6 A3 L L LLL X D1 Write Data D1 n+7 A4 L L LLL X D2 Write Data D2 5313 tbl 18 |
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