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AN131 Datasheet(PDF) 6 Page - Silicon Laboratories |
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AN131 Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 16 page AN131 6 Rev. 1.3 Timer 1, Timer 2, Timer 3, or Timer 4 as its baud rate source. UART1 no longer requires an external crystal for baud rate generation when used with the calibrated 24.5 MHz internal oscillator. Due to these changes, the baud rate calculation equations have changed. UART1 supports using Timer 1 as its baud rate source. Hardware address decoding, synchronous mode, and fixed baud rate mode are not supported by UART1. Note that SFRPAGE should be set to UART0_PAGE or UART1 PAGE before accessing any UART registers. Be aware that the timer regis- ters may not appear on the same page as the UART registers. SFRPAGE should also be set to the proper UART page prior to calls to ‘printf’ or to other input/output stream functions to direct the operations to UART0 or UART1. Timers For Timer 0 and Timer 1, an additional prescaler has been added which allows them to be clocked from SYSCLK, SYSCLK divided by 4, SYSCLK divided by 12, or SYSCLK divided by 48. Timer 0 and Timer 1 SFRs are located on the “TIM- ER01_PAGE” SFR page. Timer 2, Timer 3, and Timer 4 on the ‘F12x are enhanced forms of the equivalent ‘F02x timers. These new timers support output toggle mode, and down count capability. For more information on these timers, please refer to the C8051F12x data- sheet. Note that SFRPAGE should be set to TMR2_PAGE, TMR3_PAGE, or TMR4_PAGE before any reads or writes to Timer 2, 3, or 4 regis- ters, respectively. Programmable Counter Array (PCA) In the ‘F12x, an additional capture/compare mod- ule was added for a total of 6 capture/compare modules. Note that SFRPAGE should be set to PCA0_PAGE before any reads or writes to PCA0 registers. JTAG The JTAG device ID has changed for the ‘F12x series. See the JTAG section of the ‘F12x datasheet for details on the JTAG interface. |
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