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SL23EP04 Datasheet(PDF) 8 Page - Silicon Laboratories |
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SL23EP04 Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 16 page May 15, 2008 Page 8 of 15 SL23EP04 Switching Electrical Characteristics (I-Grade and VDD=3.3V – Cont.) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C Output Duty Cycle DC3 CL=15pF, Fout=66 MHz, all versions Measured at VDD/2 45 50 55 % Output Duty Cycle DC4 CL=15pF, Fout=133 MHz, all versions Measured at VDD/2 45 50 55 % Output Duty Cycle DC5 CL=15pF, Fout=166 MHz, all versions Measured at VDD/2 45 50 55 % Output Rise/Fall Time tr/f1 CL=30pF, -1 and -2 versions, measured from 0.8V to 2.0V - - 2.2 ns Output Rise/Fall Time tr/f2 CL=15pF, -1 and -2 versions, measured from 0.8V to 2.0V - - 1.5 ns Output Rise/Fall Time tr/f3 CL=30pF -1H and -2H version, measured from 0.8V to 2.0V - - 1.5 ns Output Rise/Fall Time tr/f4 CL=15pF -1H and -2H version, measured from 0.8V to 2.0V - - 1.2 ns Output-to-Output Skew on Same Bank SKW1 -1 and -2 measured at VDD/2 and outputs are equally loaded - 70 150 ps Output-to-Output Skew on Same Bank SKW2 -1H and -2H measured at VDD/2 and outputs are equally loaded - 60 125 ps Output-to-Output Skew Between Bank A and B SKW3 -1 and -2 measured at VDD/2 and outputs are equally loaded - 110 250 ps Output-to-Output Skew Between Bank A and B SKW4 -1H and -2H measured at VDD/2 and outputs are equally loaded - 90 200 ps Device-to-Device Skew SKW5 All versions, measured at VDD/2 and outputs are equally loaded - 150 400 ps Input-to-Output Delay Dt All versions, CLKIN to FBK rising edge, measured at VDD/2 and outputs are equally loaded -200 +/-70 200 ps Cycle-to-Cycle Jitter (-1 and, -1H Versions) CCJ1 Fout=66.6 MHz and CL=15pF - - 100 ps Fout=133.3MHz and CL=15pF - - 100 ps Fout=66.6 MHz and CL=30pF - - 100 ps |
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