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S-77101BXX-I8T1U4 Datasheet(PDF) 7 Page - Seiko Instruments Inc |
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S-77101BXX-I8T1U4 Datasheet(HTML) 7 Page - Seiko Instruments Inc |
7 / 40 page POWER SEQUENCER Rev.1.0_01 S-77100/77101 Series 7 Electrical Characteristics Table 6 (Ta = −40°C to +85°C, VDD = 2.2 V to 5.5 V, VSS = 0 V unless otherwise specified) Item Symbol Applied Pin Condition Min. Typ.*1 Max. Unit Operation power supply voltage VDD VDD − 2.2 − 5.5 V Current consumption 1 (Off period) IDD1 VDD VDD = 3.3 V, ON pin, OFF _______ pin*2 = VSS, ENBL_x pin = Open − 3.0 6.0 μA Current consumption 2 (Power-good period) IDD2 VDD VDD = 3.3 V, ON pin, OFF _______ pin*2 = VDD, ENBL_x pin = Open − 3.0 6.0 μA Current consumption 3 (On-sequence period, off-sequence period) IDD3 VDD VDD = 3.3 V, ON pin, OFF _______ pin*2 = VDD or VSS, ENBL_x pin = Open − − 8.0 μA Low voltage detection voltage VUVLO VDD − 1.85 2.0 2.13 V High level input leakage current IIZH ON, OFF _______ *2 VIN = VDD −0.3 − 0.3 μA Low level input leakage current IIZL ON, OFF _______ *2 VIN = VSS −0.3 − 0.3 μA Input voltage (When Schmitt trigger input is selected) VIL ON, OFF _______ *2 − VSS − 0.3 − 0.2 × VDD V VIH ON, OFF _______ *2 − 0.8 × VDD − VDD + 0.3 V Input threshold voltage (When comparator input is selected) VIT_ON ON, OFF _______ *2 − 0.3 0.8 1.3 V High level output leakage current*3 IOZH ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 VOUT = VDD −0.3 − 0.3 μA Low level output leakage current*3 IOZL ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 VOUT = VSS −0.3 − 0.3 μA Low level output voltage VOL ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 IOL = 2.0 mA − − 0.4 V High level output voltage*5 VOH ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 IOH = −0.4 mA 0.8 × VDD − − V Delay time*6 tDLY ENBL_A, ENBL_B, ENBL_C, ENBL_D*4 Ta = +25°C, VDD = 3.3 V, The period from ENBL_A pin rising to ENBL_B pin rising, CDLY = 10 nF, The number of times of CDLY charge and discharge = 4 times 40 45 50 ms *1. Typ. values are the values at the time of Ta = +25°C. *2. The S-77101 Series only *3. When Nch open-drain output is selected as the option. *4. The S-77100 Series only *5. When CMOS output is selected as the option. *6. The delay time varies depending on the usage environment. Perform thorough evaluation using the actual application to set the constant. Refer to " Relation between Delay Time and External Capacitors" for details. |
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