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SDP600-500Pa Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part # SDP600-500Pa
Description  Accuracy better than 0.2% FS near zero
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SDP600-500Pa Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

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Version 1.9 – July 2015
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3. Interface Specifications
The serial interface of the SDP600 series is compatible
with I2C interfaces. For detailed specifications of the I2C
protocol, see The I2C Bus Specification (source: NXP).
3.1
Interface connection – external
components
Bi-directional bus lines are implemented by the devices
(master and slave) using open-drain output stages and a
pull-up resistor connected to the positive supply voltage.
The recommended pull-up resistor value depends on the
system setup (capacitance of the circuit or cable and bus
clock frequency). In most cases, 10 kΩ is a reasonable
choice.
The capacitive loads on SDA and SCL line have to be the
same. It is important to avoid asymmetric capacitive loads.
I2C Transmission Start Condition
SDA
SCL
VDD
master
slave (SDP600)
Rp
Rp
Both bus lines, SDA and SCL, are bi-directional and therefore
require an external pull-up resistor.
3.2
I2C Address
The I2C address consists of a 7-digit binary value. By
default, the I2C address is set to 64 (binary: 1000 000).
The address is always followed by a write bit (0) or read
bit (1). The default hexadecimal I2C header for read
access to the sensor is therefore h81.
3.3
Transfer sequences
Transmission START Condition (S): The START condi-
tion is a unique situation on the bus created by the master,
indicating to the slaves the beginning of a transmission
sequence (the bus is considered busy after a START).
I2C Transmission Start Condition
S
START condition
SDA
SCL
A HIGH to LOW transition on the SDA line while SCL is HIGH
Transmission STOP Condition (P): The STOP condition
is a unique situation on the bus created by the master,
indicating to the slaves the end of a transmission
sequence (the bus is considered free after a STOP).
I2C Transmission Stop Condition
P
STOP condition
SDA
SCL
A LOW to HIGH transition on the SDA line while SCL is HIGH.
Acknowledge (ACK) / Not Acknowledge (NACK): Each
byte (8 bits) transmitted over the I2C bus is followed by an
acknowledge condition from the receiver. This means that
after the master pulls SCL low to complete the
transmission of the 8th bit, SDA will be pulled low by the
receiver during the 9th bit time. If after transmission of the
8th bit the receiver does not pull the SDA line low, this is
considered to be a NACK condition.
If an ACK is missing during a slave to master transmission,
the slave aborts the transmission and goes into idle mode.
I2C Acknowledge / Not Acknowledge
ACK
SCL
R/_W
D7
D0
ACK
SDA
not acknowledge
acknowledge
Each byte is followed by an acknowledge or a not
acknowledge, generated by the receiver
Handshake procedure (Hold Master): In a master-slave
system, the master dictates when the slaves will receive or
transmit data. However, in some situations a slave device
may need time to store received data or prepare data to
be transmitted. Therefore, a handshake procedure is
required to allow the slave to indicate termination of
internal processing.
I2C Hold Master
ACK
SCL
R/_W
D7
D0
ACK
SDA
Hold master:
SCK line pulled LOW
data ready: SCK line released
After the SCL pulse for the acknowledge signal, the SDP600
series sensor (slave) can pull down the SCL line to force the
master into a wait state. By releasing the SCL line, the sensor
indicates that its internal processing is completed and
transmission can resume. (The bold lines indicate that the
sensor controls the SDA/SCL lines.)


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