Philips Semiconductors

Product specification

TrenchMOS

™ transistor

BUK9606-55A

Logic level FET

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode logic

SYMBOL

PARAMETER

MAX.

UNIT

level field-effect power transistor in a

plastic envelope suitable for surface

V

DS

Drain-source voltage

55

V

mounting. Using ’trench’ technology

I

D

Drain current (DC)

75

A

the device features very low on-state

P

tot

Total power dissipation

230

W

resistance. It is intended for use in

T

j

Junction temperature

175

˚C

automotive and general purpose

R

DS(ON)

Drain-source on-state

switching applications.

resistance

V

6.3

m

Ω

V

5.8

m

Ω

PINNING - SOT404

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain (no connection

possible)

3

source

mb

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

-

55

V

V

DGR

Drain-gate voltage

R

-55

V

±V

GS

Gate-source voltage

-

-

10

V

±V

GSM

Non-repetitive gate-source voltage

t

-

15

V

I

D

Drain current (DC)

T

-

75

A

I

D

Drain current (DC)

T

-

75

A

I

DM

Drain current (pulse peak value)

T

-

240

A

P

tot

Total power dissipation

T

-

230

W

T

Storage & operating temperature

-

- 55

175

˚C

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R

th j-mb

Thermal resistance junction to

-

-

0.65

K/W

mounting base

R

th j-a

Thermal resistance junction to

Minimum footprint, FR4

50

-

K/W

ambient

board

d

g

s

13

mb

2

January 1999

1

Rev 1.000