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BUK9635-100A Datasheet(PDF) 1 Page - NXP Semiconductors |
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BUK9635-100A Datasheet(HTML) 1 Page - NXP Semiconductors |
1 / 7 page Philips Semiconductors Product specification TrenchMOS ™ transistor BUK9635-100A Logic level FET GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT level field-effect power transistor in a plastic envelope suitable for surface V DS Drain-source voltage 100 V mounting. Using ’trench’ technology I D Drain current (DC) 40 A the device features very low on-state P tot Total power dissipation 150 W resistance. It is intended for use in T j Junction temperature 175 ˚C automotive and general purpose R DS(ON) Drain-source on-state switching applications. resistance V GS = 5 V 35 m Ω V GS = 10 V 34 m Ω PINNING - SOT404 PIN CONFIGURATION SYMBOL PIN DESCRIPTION 1 gate 2 drain (no connection possible) 3 source mb drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source voltage - - 100 V V DGR Drain-gate voltage R GS = 20 kΩ - 100 V ±V GS Gate-source voltage - - 10 V ±V GSM Non Repetive gate-source voltage - - 15 V I D Drain current (DC) T mb = 25 ˚C - 40 A I D Drain current (DC) T mb = 100 ˚C - 29 A I DM Drain current (pulse peak value) T mb = 25 ˚C - 133 A P tot Total power dissipation T mb = 25 ˚C - 150 W T stg, Tj Storage & operating temperature - - 55 175 ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction to - - 1.01 K/W mounting base R th j-a Thermal resistance junction to Minimum footprint, FR4 50 - K/W ambient board d g s 13 mb 2 August 1999 1 Rev 1.000 |
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Similar Description - BUK9635-100A |
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