bq2205LY

SLUS581 − FEBRUARY 2004

3

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ELECTRICAL CHARACTERISTICS

(TA = 25°C, VCC(min) ≤ VCC ≤ VCC(max) unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCC supply current, ICC(vcc)

VCC > VCC(MIN)

CE = low

CECONX = 0 mA

210

500

µA

Backup Battery Supply Current, ICC(BC)

VBC > VBC(MIN), VCC = 0 V

CE = low

CECONX = 0 mA

50

150

nA

Output voltage (VOUT)

I(VOUT) = 80 mA, VCC > V(SO)

Vcc−0.3

Output voltage (VOUT)

I(VOUT)= 100µ A, VCC < V(SO)

VBC−0.3

Power fail detect voltage, VPFD

2.85

2.9

2.95

Supply switch-over voltage, VSO

VBC > V(PFD)

VPFD

V

Supply switch-over voltage, VSO

VBC < V(PFD)

VBC

V

RST output voltage

I(RST) = 1 mA

0.4

BW output voltage

I(BW)= 1 mA

0.4

Input leakage current on A and CE pins

−1

1

µA

Voh CEcon1,2

Ioh = 0.5 mA

2.4

Vol CEcon1,2

Iol = 2.0 mA

0.4

V

Battery warning level VBW

(1)

0.677xVCC

V

Capacitance

Output capacitance

VOUT = 0 V

7

pF

Input capacitance

VOUT = 0 V

5

pF

Power-Down and Power-Up Timing, Refer to Figure 1 through 3

VCC slew rate fall time, tF

3.0 V to 0.0 V

300

s

VCC slew rate rise time, tR

VSO to VPFD(max)

100

µs

VPFD to RST active, tRST

(reset active timeout period)

30

85

ms

Chip-enable recovery time, tCER

(2)

30

85

ms

Chip-enable propagation delay time to external

SRAM, tCED

See Figure 2

15

25

ns

Push-button low time, tPBL

RST pin

1

µs

(1)

Battery warning level is detected on power up and the BW pin is latched at tCER time after VCC passes through VPFD on power up.

(2)

Time during which external SRAM is write protected after VCC passes through VPFD on power up.