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BQ296112DSGT Datasheet(PDF) 7 Page - Texas Instruments |
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BQ296112DSGT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 33 page  7 bq2961, bq2962 www.ti.com SLUSBU5D – NOVEMBER 2013 – REVISED JANUARY 2017 Product Folder Links: bq2961 bq2962 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated (1) Specified by design. Not 100% tested in production. 7.5 Electrical Characteristics Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to +110°C, and VDD = 3 V to 15 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Protection Thresholds VOV V(PROTECT) Overvoltage Detection RIN = 1 kΩ Applicable Voltage: 3.85 V to 4.6 V in 50 mV steps V VHYS OV Detection Hysteresis 250 300 400 mV VOA OV Detection Accuracy TA = 25°C –10 10 mV VOADRIFT OV Detection Accuracy Across Temperature TA = –40°C –40 40 mV TA = 0°C –20 20 mV TA = 60°C –24 24 mV TA = 110°C –54 54 mV TA = 110°C –54 54 mV Supply and Leakage Current IDD Supply Current with REG on (Vn – Vn-1) = 2 V to 4.15 V, n = 1 to 4, VDD = top Vn voltage (V1 – VSS) > VUVREG , IREG = 0 mA, TA = 0°C to 60°C 4 6 µA TA = –40°C to 110°C 8 µA IDD Supply Current with REG off (Vn – Vn-1) = 2 V to 4.15 V, n = 1 to 4, VDD = top Vn voltage (V1 – VSS) < VUVREG TA = 0°C to 60°C 1 2 µA TA = –40°C to 110°C 4 µA IIN Input Current at Vx Pins (Vn – Vn-1) = (V1 – VSS) = 3.8 V, VDD = top Vn voltage, TA = 25°C –0.1 0.1 µA Output Drive OUT, CMOS Active High VOUT Output Drive Voltage, Active High (Vn – Vn-1) or (V1 – VSS) > VOV, IOH = 100 µA, VDD = top Vn voltage 6 7 8 V If three of four cells are short circuited, only one cell remains powered and > VOV, VDD = Vn (the remaining cell voltage), IOH = 100 µA VDD – 0.3 V (Vn – Vn-1) and (V1 – VSS) < VOV, VDD = sum of the cell stack voltage, IOL = 100 µA measured into OUT pin 250 400 mV IOUTH OUT Source Current (during OV) (Vn – Vn-1), (V3 – V2), or (V1 – VSS) > VOV, VDD = top Vn voltage, forced OUT = 0 V, measured out of OUT pin 4.5 mA IOUTL OUT Sink Current (no OV) (Vn – Vn-1) and (V1 – VSS) < VOV, VDD = top Vn voltage, forced OUT = VDD, measured into OUT pin. Pull-up resistor RPU = 5 kΩ to VDD 0.5 14 mA Internal Fixed Delay Timer tDELAY OV Delay Time(1) Internal Fixed Delay, 3 second delay option 2.4 3 3.6 s Internal Fixed Delay, 4 second delay option 3.2 4 4.8 s Internal Fixed Delay, 5.5 second delay option 4.4 5.5 6.6 s Internal Fixed Delay, 6.5 second delay option 5.2 6.5 7.8 s tDELAY_CTM Fault Detection Delay Time in Test Mode OV Delay Time Internal Fixed delay 15 ms |
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