1

VDD

10

SENSE

2

CWD

9

RESET

3

SET0

8

WDO

4

CRST

7

WDI

5

GND

6

SET1

Not to scale

Pad

3

TPS3850-Q1

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SBVS264 – JANUARY 2017

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5 Pin Configuration and Functions

DRC Package

3-mm × 3-mm VSON-10

Top View

Pin Functions

PIN

DESCRIPTION

NAME

NO.

I/O

CRST

4

I

Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout

period. This pin can also be connected by a 10-kΩ pullup resistor to VDD, or left unconnected (NC) for various

factory-programmed reset timeout options; see the CRST Delay section.

When using an external capacitor, use Equation 3 to determine the reset timeout.

CWD

2

I

Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin

and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected

(NC) further enables the selection of the preset watchdog timeouts; see the Timing Requirements table.

When using a capacitor, the TPS3850-Q1 determines the window watchdog upper boundary with Equation 6.

The lower watchdog boundary is set by the SET pins, see Table 6 and the CWD Functionality section for

additional information.

GND

5

—

Ground pin

RESET

9

O

Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to VDD. RESET goes low when the voltage at

When the voltage level at the SENSE pin is within the normal operating range, the RESET timeout counter

starts. At timer completion, RESET goes high. During startup, the state of RESET is undefined below the

SENSE

10

I

SENSE input to monitor the voltage rail. Connect this pin to the supply rail that must be monitored.

SET0

3

I

Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;

see the Timing Requirements table.

SET1

6

I

Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;

see the Timing Requirements table.

VDD

1

I

Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended.

WDI

7

I

When the watchdog is not in use, the SETx pins can be used to disable the watchdog. The input at WDI is

ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is

disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND.

WDO

8

O

Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to VDD. WDO goes low (asserts) when a

watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO

impedance state.

Thermal pad

—

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.