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AD8139ARDZ Datasheet(PDF) 8 Page - Analog Devices |
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AD8139ARDZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 27 page  Data Sheet AD8139 Rev. C | Page 7 of 26 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage 12 V VOCM ±VS Power Dissipation See Figure 4 Input Common-Mode Voltage ±VS Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +125°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages. Table 4. Package Type θJA Unit 8-Lead SOIC with EP/4-Layer 70 °C/W 8-Lead LFCSP/4-Layer 70 °C/W Maximum Power Dissipation The maximum safe power dissipation in the AD8139 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8139. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices potentially causing failure. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and the internal common-mode feedback loop. The internal resistor tap used in the common-mode feedback loop places a 1 kΩ differential load on the output. RMS output voltages should be considered when dealing with ac signals. Airflow reduces θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle (EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP (θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA values are approximations. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –40 –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) SOIC AND LFCSP Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION |
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