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SA56614-44 Datasheet(PDF) 7 Page - NXP Semiconductors |
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SA56614-44 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 14 page Philips Semiconductors Product data SA56614-XX CMOS system reset 2001 Jun 19 7 TECHNICAL DESCRIPTION The SA56614-XX is a CMOS device designed to monitor the system’s power source and provide a system reset function in the event the supply voltage sags below an acceptable level for the system to reliably operate. The SA56614 generates a compatible reset signal for a wide variety of microprocessor and logic systems. The device can operate at voltages up to 12 volts. The series includes several versions providing precision threshold voltage reset values of 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2, 4.6, and 4.7 V. The reset threshold incorporates a typical hysteresis of (VS × 0.05) volts to prevent erratic resets from being generated. The SA56614 operates at very low supply currents, typically 0.25 µA, while offering a high precision of threshold detection ( ±2%). The output of the SA56614 incorporates an active Totem-Pole output topology comprised of complimentary P-Channel and N-Channel FETs. A P-Channel FET is on the high supply side and when ON pulls the output to or near the VDD supply voltage from which output source current can be obtained. A complimentary N-Channel FET is on the low or ground side, and actively pulls the output LOW or to ground with the capability of sinking current into the output. Both devices supply system reset signals. The user should keep in mind, when connecting the SA56614 to a system, the effect of supplying source current from the output of the SA56614 on the system. This is of particular importance where the SA56614 is operated from a different supply source than the rest of the system. Figure 12 is a functional block diagram of the SA56614. The internal reference source voltage (VREF) is typically 0.8 V over the operating temperature range. The reference voltage is connected to the non-inverting input of the threshold comparator while the inverting input monitors the supply voltage through a resistor divider network made up of R1, R2, and R3. The output of the threshold comparator drives the totem-pole output stage of the device. When the supply voltage sags to the threshold detection voltage, the resistor divider network supplies a voltage to the inverting input of the threshold comparator which is less than that of VREF, causing the output of the comparator to adopt a HIGH output state. This causes the high side P-Channel FET of the Totem-Pole output stage to turn OFF while simultaneously turning the low side N-Channel FET from OFF to an active ON state, pulling the output to a LOW voltage state. The device adheres to a true input/output logic protocol. The output goes to a LOW voltage state when input is LOW (below VS) and the output HIGH goes to a HIGH voltage state when the input is HIGH (above VS). The low side N-Channel FET (TR3) establishes threshold hysteresis by turning ON whenever the threshold comparator’s output goes to a HIGH state (when VDD sags to or below the threshold level). TR3’s turning ON causes additional current to flow through resistors R1, and R2 causing the inverting input of the threshold comparator to be pulled even lower. For the comparator to reverse its output polarity and turn OFF TR3, the VDD source voltage must overcome this additional pull-down voltage present on the comparator’s inverting input. The differential voltage required to do this establishes the hysteresis voltage of the sensed threshold voltage. Typically it is (VS × 0.05) volts. When the VDD voltage sags and is at or below the Detection Threshold (VSL), the device will assert a Reset LOW output at or very near ground potential. As the VDD voltage rises from (VDD < VSL) to VSH or higher, the reset is released and the output follows VDD. Conversely, decreases in VDD from (VDD > VSL) to VSL or lower cause the output to be pulled to ground. Hysteresis Voltage = Release Voltage – Detection Threshold Voltage VHYS = VSH – VSL where: VSH = VSL + VHYS ≅ VREF(R1 + R2) / R2 VSL = VREF(R1 + R2 + R3) / (R2 + R3) When VDD drops below the minimum operating voltage, typically less than 0.95 volts, the output is undefined and output reset low assertion is not guaranteed. At this level of VDD the output will try to rise to VDD. The VREF voltage is typically 0.8 V. The devices are fabricated using a high resistance CMOS process and utilize high resistance R1, R2, and R3 values requiring very small amounts of current. This combination achieves very efficient low power performance over the full operating temperature. SL01353 VDD VSS VREF NE56614-XX VOUT 1 R2 R1 R R3 TR1 TR2 TR3 3 2 Figure 12. Functional diagram |
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