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ADuCM363BCPZ128RL7 Datasheet(PDF) 9 Page - Analog Devices |
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ADuCM363BCPZ128RL7 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 24 page  Data Sheet ADuCM362/ADuCM363 Rev. 0 | Page 9 of 24 Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL INPUTS All digital inputs Input Leakage Current Digital inputs except for the RESET, SWCLK, and SWDIO pins Logic 1 VINH = IOVDD or VINH = 1.8 V 140 μA Internal pull-up disabled 1 nA Logic 0 VINL = 0 V 160 μA Internal pull-up disabled 10 nA Input Leakage Current RESET, SWCLK, and SWDIO pins Logic 1 140 μA Logic 0 160 μA Input Capacitance1 10 pF Logic Input Voltage Low, VINL 0.2 × IOVDD V High, VINH 0.7 × IOVDD V Logic Output Voltage High, VOH ISOURCE = 1 mA IOVDD − 0.4 V Low, VOL ISINK = 1 mA 0.4 V CRYSTAL OSCILLATOR1 32.768 kHz crystal inputs Logic Input Voltage, XTALI Only15 Low, VINL 0.8 V High, VINH 1.7 V XTALI Capacitance 6 pF XTALO Capacitance 6 pF ON-CHIP LOW POWER OSCILLATOR Oscillator Frequency 32.768 kHz Accuracy −30 ±10 +30 % ON-CHIP HIGH FREQUENCY OSCILLATOR Oscillator Frequency 16 MHz Accuracy −40°C to +125°C −1.8 +1.4 % Long Term Stability5 0.8 °C/1000 Hr PROCESSOR CLOCK RATE1 Nine programmable core clock selections within specified range 0.0625 0.5 16 MHz Using an External Clock 0.032768 16 MHz PROCESSOR START-UP TIME1 At Power-On Includes kernel power-on execution time 41 ms After Reset Event Includes kernel power-on execution time 1.44 ms From Processor Power-Down (Mode 1, Mode 2, and Mode 3) fCLK is the Cortex-M3 core clock 3 to 5 fCLK From Total Halt or Hibernate Mode (Mode 4 or Mode 5) 30.8 μs |
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