Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

ADSP-BF704KCPZ-4 Datasheet(PDF) 10 Page - Analog Devices

Part # ADSP-BF704KCPZ-4
Description  Instruction set compatible with previous Blackfin products
Download  116 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF704KCPZ-4 Datasheet(HTML) 10 Page - Analog Devices

Back Button ADSP-BF704KCPZ-4 Datasheet HTML 6Page - Analog Devices ADSP-BF704KCPZ-4 Datasheet HTML 7Page - Analog Devices ADSP-BF704KCPZ-4 Datasheet HTML 8Page - Analog Devices ADSP-BF704KCPZ-4 Datasheet HTML 9Page - Analog Devices ADSP-BF704KCPZ-4 Datasheet HTML 10Page - Analog Devices ADSP-BF704KCPZ-4 Datasheet HTML 11Page - Analog Devices ADSP-BF704KCPZ-4 Datasheet HTML 12Page - Analog Devices ADSP-BF704KCPZ-4 Datasheet HTML 13Page - Analog Devices ADSP-BF704KCPZ-4 Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 116 page
background image
Rev. A
|
Page 10 of 116
|
September 2015
ADSP-BF700/701/702/703/704/705/706/707
General-Purpose Timers
There is one GP timer unit, and it provides eight general-pur-
pose programmable timers. Each timer has an external pin that
can be configured either as a pulse width modulator (PWM) or
timer output, as an input to clock the timer, or as a mechanism
for measuring pulse widths and periods of external events.
These timers can be synchronized to an external clock input on
the TIMER_TMRx pins, an external TIMER_CLK input pin, or
to the internal SCLK0.
These timer units can be used in conjunction with the UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
The GP timers can generate interrupts to the processor core,
providing periodic events for synchronization to either the sys-
tem clock or to external signals. Timer events can also trigger
other peripherals through the TRU (for instance, to signal a
fault). Each timer may also be started and/or stopped by any
TRU master without core intervention.
Core Timer
The processor core also has its own dedicated timer. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generating periodic operating
system interrupts.
Watchdog Timer
The core includes a 32-bit timer, which may be used to imple-
ment a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state, through generation of a hardware reset, nonmaskable
interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. The programmer initial-
izes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts down to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software that would normally reset the
timer has stopped running due to an external noise condition or
software error.
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in its
timer control register that is set only upon a watchdog-gener-
ated reset.
Serial Ports (SPORTs)
Two synchronous serial ports (comprised of four half-SPORTs)
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’ audio
codecs, ADCs, and DACs. Each half-SPORT is made up of two
data lines, a clock, and frame sync. The data lines can be pro-
grammed to either transmit or receive and each data line has a
dedicated DMA channel.
Serial port data can be automatically transferred to and from
on-chip memory/external memory through dedicated DMA
channels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this
configuration, one SPORT provides two transmit signals while
the other SPORT provides the two receive signals. The frame
sync and clock are shared.
Serial ports operate in six modes:
• Standard DSP serial mode
•Multichannel (TDM) mode
•I2S mode
•Packed I2S mode
• Left-justified mode
•Right-justified mode
General-Purpose Counters
A 32-bit counter is provided that can operate in general-pur-
pose up/down count modes and can sense 2-bit quadrature or
binary codes as typically emitted by industrial drives or manual
thumbwheels. Count direction is either controlled by a level-
sensitive input pin or by two edge detectors.
A third counter input can provide flexible zero marker support
and can alternatively be used to input the push-button signal of
thumbwheel devices. All three pins have a programmable
debouncing circuit.
Internal signals forwarded to a GP timer enable this timer to
measure the intervals between count events. Boundary registers
enable auto-zero operation or simple system warning by inter-
rupts when programmed count values are exceeded.
Parallel Peripheral Interface (PPI)
The processor provides a parallel peripheral interface (PPI) that
supports data widths up to 18 bits. The PPI supports direct con-
nection to TFT LCD panels, parallel analog-to-digital and
digital-to-analog converters, video encoders and decoders,
image sensor modules, and other general-purpose peripherals.
The following features are supported in the PPI module:
• Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits,
16 bits, and 18 bits per clock.
• Various framed, non-framed, and general-purpose operat-
ing modes. Frame syncs can be generated internally or can
be supplied by an external device.
• ITU-656 status word error detection and correction for
ITU-656 receive modes and ITU-656 preamble and status
word decode.
• Optional packing and unpacking of data to/from 32 bits
from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is
enabled, endianness can be configured to change the order
of packing/unpacking of bytes/words.
• RGB888 can be converted to RGB666 or RGB565 for trans-
mit modes.
•Various de-interleaving/interleaving modes for receiv-
ing/transmitting 4:2:2 YCrCb data.
•Configurable LCD data enable (DEN) output available on
Frame Sync 3.


Similar Part No. - ADSP-BF704KCPZ-4

ManufacturerPart #DatasheetDescription
logo
Analog Devices
ADSP-BF504 AD-ADSP-BF504 Datasheet
4Mb / 80P
   Blackfin Embedded Processor
Rev. PrC
ADSP-BF504F AD-ADSP-BF504F Datasheet
4Mb / 80P
   Blackfin Embedded Processor
Rev. PrC
ADSP-BF506F AD-ADSP-BF506F Datasheet
1Mb / 75P
   ADSP-BF506F EZ-KIT Lite짰 Evaluation System Manual
Revision 1.0 December2009
ADSP-BF506F AD-ADSP-BF506F Datasheet
4Mb / 80P
   Blackfin Embedded Processor
Rev. PrC
ADSP-BF512 AD-ADSP-BF512 Datasheet
1Mb / 62P
   Blackfin Embedded Processor
Rev. PrE
More results

Similar Description - ADSP-BF704KCPZ-4

ManufacturerPart #DatasheetDescription
logo
Freescale Semiconductor...
MC912DG128ACPVE FREESCALE-MC912DG128ACPVE Datasheet
2Mb / 478P
   Upward compatible with M68HC11 instruction set
logo
SyncMOS Technologies,In...
SM59R02G1 SYNCMOS-SM59R02G1 Datasheet
786Kb / 57P
   Instruction-set compatible with MCS-51
SM59A16U1 SYNCMOS-SM59A16U1 Datasheet
2Mb / 146P
   Instruction-set compatible with MCS-51
logo
Freescale Semiconductor...
S9S08DZ32F1CLH FREESCALE-S9S08DZ32F1CLH Datasheet
2Mb / 416P
   HC08 instruction set with added BGND instruction
MC9S08GW64 FREESCALE-MC9S08GW64_11 Datasheet
1,011Kb / 42P
   HC08 instruction set with added BGND instruction
logo
SINOWEALTH Electronic L...
SH79F1617 SINOWEALTH-SH79F1617 Datasheet
1Mb / 99P
   8bits micro-controller with Pipe-line structured 8051 compatible instruction set
V2.0
logo
STMicroelectronics
STLUX385 STMICROELECTRONICS-STLUX385 Datasheet
171Kb / 10P
   Extended instruction set
February 2013 Rev 2
STM8S007C8 STMICROELECTRONICS-STM8S007C8 Datasheet
1Mb / 92P
   Extended instruction set
March 2015 Rev 5
STM8S005C6 STMICROELECTRONICS-STM8S005C6 Datasheet
1Mb / 97P
   Extended instruction set
March 2015 Rev 4
logo
Samsung semiconductor
S3C72G9 SAMSUNG-S3C72G9 Datasheet
1,011Kb / 96P
   SAM47 INSTRUCTION SET
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com