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ADSP-BF704KCPZ-4 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-BF704KCPZ-4 Datasheet(HTML) 10 Page - Analog Devices |
10 / 116 page Rev. A | Page 10 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 General-Purpose Timers There is one GP timer unit, and it provides eight general-pur- pose programmable timers. Each timer has an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input on the TIMER_TMRx pins, an external TIMER_CLK input pin, or to the internal SCLK0. These timer units can be used in conjunction with the UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The GP timers can generate interrupts to the processor core, providing periodic events for synchronization to either the sys- tem clock or to external signals. Timer events can also trigger other peripherals through the TRU (for instance, to signal a fault). Each timer may also be started and/or stopped by any TRU master without core intervention. Core Timer The processor core also has its own dedicated timer. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generating periodic operating system interrupts. Watchdog Timer The core includes a 32-bit timer, which may be used to imple- ment a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state, through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initial- izes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts down to zero from the pro- grammed value. This protects the system from remaining in an unknown state where software that would normally reset the timer has stopped running due to an external noise condition or software error. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in its timer control register that is set only upon a watchdog-gener- ated reset. Serial Ports (SPORTs) Two synchronous serial ports (comprised of four half-SPORTs) provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ audio codecs, ADCs, and DACs. Each half-SPORT is made up of two data lines, a clock, and frame sync. The data lines can be pro- grammed to either transmit or receive and each data line has a dedicated DMA channel. Serial port data can be automatically transferred to and from on-chip memory/external memory through dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. In this configuration, one SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in six modes: • Standard DSP serial mode •Multichannel (TDM) mode •I2S mode •Packed I2S mode • Left-justified mode •Right-justified mode General-Purpose Counters A 32-bit counter is provided that can operate in general-pur- pose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. Count direction is either controlled by a level- sensitive input pin or by two edge detectors. A third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumbwheel devices. All three pins have a programmable debouncing circuit. Internal signals forwarded to a GP timer enable this timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by inter- rupts when programmed count values are exceeded. Parallel Peripheral Interface (PPI) The processor provides a parallel peripheral interface (PPI) that supports data widths up to 18 bits. The PPI supports direct con- nection to TFT LCD panels, parallel analog-to-digital and digital-to-analog converters, video encoders and decoders, image sensor modules, and other general-purpose peripherals. The following features are supported in the PPI module: • Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, and 18 bits per clock. • Various framed, non-framed, and general-purpose operat- ing modes. Frame syncs can be generated internally or can be supplied by an external device. • ITU-656 status word error detection and correction for ITU-656 receive modes and ITU-656 preamble and status word decode. • Optional packing and unpacking of data to/from 32 bits from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is enabled, endianness can be configured to change the order of packing/unpacking of bytes/words. • RGB888 can be converted to RGB666 or RGB565 for trans- mit modes. •Various de-interleaving/interleaving modes for receiv- ing/transmitting 4:2:2 YCrCb data. •Configurable LCD data enable (DEN) output available on Frame Sync 3. |
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