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ADF4355-3BCPZ Datasheet(PDF) 4 Page - Analog Devices |
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ADF4355-3BCPZ Datasheet(HTML) 4 Page - Analog Devices |
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4 / 35 page  Data Sheet ADF4355-3 Rev. A | Page 3 of 34 SPECIFICATIONS AVDD = DVDD = VRF = VP = VVCO = VREGVCO = 3.3 V ± 4.5%, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments REFINA/REFINB CHARACTERISTICS Input Frequency REFIN For f < 10 MHz, ensure that the slew rate > 21 V/µs Single-Ended Mode 10 250 MHz Differential Mode 10 600 MHz Doubler Enabled 100 MHz Doubler is set in Register 4, Bit DB26 Input Sensitivity Single-Ended Mode 0.4 AVDD V p-p REFINA biased at AVDD/2; ac coupling ensures AVDD/2 bias Differential Mode 0.4 1.8 V p-p LVDS and LVPECL compatible, REFINA/ REFINB biased at 2.1 V; ac coupling ensures 2.1 V bias Input Capacitance Single-Ended Mode 6.9 pF Differential Mode 1.4 pF Input Current ±60 µA Single-ended reference programmed ±250 µA Differential reference programmed Phase Detector Frequency 125 MHz CHARGE PUMP (CP) Charge Pump Current, Sink/Source ICP RSET = 5.1 kΩ High 4.8 mA Low 0.3 mA RSET Range 5.1 kΩ Fixed Current Matching 3 % 0.5 V ≤ VCP1 ≤ VP − 0.5 V ICP vs. VCP1 3 % 0.5 V ≤ VCP1 ≤ VP − 0.5 V ICP vs. Temperature 1.5 % VCP1 = 2.5 V LOGIC INPUTS 1.8 V and 3.3 V compatible Input Voltage High VINH 1.5 DVDD V Low VINL 0.6 V Input Current IINH/IINL ±1 µA Input Capacitance CIN 3.0 pF LOGIC OUTPUTS Output Voltage High VOH DVDD − 0.4 V 3.3 V output selected 1.5 1.8 V 1.8 V output selected Low VOL 0.4 V IOL2 = 500 µA Output High Current IOH 500 µA POWER SUPPLIES Analog Power AVDD 3.1515 3.3 3.4485 V 3.3 V ± 4.5% Digital Power, RF Supply, Charge Pump, and VCO Supply Voltage DVDD, VRF, VP, VVCO AVDD Voltages must equal AVDD Charge Pump Supply Current IP 3.1 5 mA DIDD + AIDD3 66 75 mA Supply current drawn by DVDD plus supply current drawn by AVDD Output Dividers See Table 6 VCO Supply Current IVCO 52 70 mA RFOUTA±/RFOUTB± Supply Current ± x RF OUT I 13/19/ 25/31 20/27/ 34/41 mA RF output stage is programmable; RFOUTB+/RFOUTB− powered off Low Power Sleep Mode 1500 µA Hardware power-down 1950 µA Software power-down |
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