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CN0269 Datasheet(PDF) 4 Page - Analog Devices |
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CN0269 Datasheet(HTML) 4 Page - Analog Devices |
4 / 12 page CN-0269 Circuit Note Rev. 0 | Page 4 of 12 For the ADG5208, RON is 160 Ω, and CD is 52 pF. The transition delay of ADG5208 is 160 ns. So, the 90% settling time of the ADG5208 is ( )( ) ns 21 pF 35 pF 52 160 100 10 ln – %) 90 ( = + Ω = 300 || SETTLE t From Equation 1, tMD = tTRANSITION – tSETTLE(90%) = 160 ns – 21 ns = 139 ns Therefore, under this circuit configuration with the ADG5208 and the ADG5236, the total extra time delay due to the digital circuits is tDD + tMD = 8 ns + 139 ns = 147 ns Actually, this digital delay of 147 ns due to the digital control circuit and part of the transition delay from multiplexer can be compensated by delaying the rising edge of the convert signal with respect to the multiplexer update signal by an amount of time equal to tDD + tMD. However, both tDD and tMD are a function of temperature, power supply voltage, and normal variations from part to part. The time margin must be enough to account for the variation and drift. For example, under this configuration with 147 ns digital delay, switching the multiplexer 100 ns to 120 ns ahead of the ADC convert signal (tAHEAD) increases the available settling time by the same amount. The optimized timing is shown in Figure 4, but was not implemented in the actual circuit in order to minimize complexity. Figure 4. Optimized Timing of Multichannel Data Acquisition Circuit MUX CTRL [0000] [0001] TO CH0 SETTLING TO CH1 CONVERSION tCONV tAHEAD tACQ ACQUISITION tS tMD tDD tSETTLE CNV STATUS [CH3:CH0] VOUT_SW |
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