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LM74CIBP-5 Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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LM74CIBP-5 Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 15 page Logic Electrical Characteristics (Continued) DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for V + = 2.65V to 3.6V for the LM74CIBP -3, V + = 3.0V to 3.6V for the LM74CIM -3 and V+ = 4.5V to 5.5V for the LM74 -5 (Note 6). Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ=+25˚C, unless otherwise noted. Symbol Parameter Conditions Typical (Note 7) Limits (Note 8) Units (Limit) I IN(0) Logical “0” Input Current V IN = 0V −0.005 −3.0 µA (min) C IN All Digital Inputs 20 pF V OH High Level Output Voltage I OH = −400 µA 2.4 V (min) V OL Low Level Output Voltage I OL =+2 mA 0.4 V (max) I O_TRI-STATE TRI-STATE Output Leakage Current V O = GND V O =V + −1 +1 µA (min) µA (max) SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for V + = 2.65V to 3.6V for the LM74CIBP -3, V + = 3.0V to 3.6V for the LM74CIM -3 and V+ = 4.5V to 5.5V for the LM74 -5 (Note 6); C L (load capacitance) on output lines = 100 pF unless otherwise specified. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits T A =TJ = +25˚C, unless otherwise noted. Symbol Parameter Conditions Typical (Note 7) Limits (Note 8) Units (Limit) t 1 SC (Clock) Period 0.16 DC µs (min) (max) t 2 CS Low to SC (Clock) High Set-Up Time 100 ns (min) t 3 CS Low to Data Out (SO) Delay 70 ns (max) t 4 SC (Clock) Low to Data Out (SO) Delay 100 ns (max) t 5 CS High to Data Out (SO) TRI-STATE 200 ns (max) t 6 SC (Clock) High to Data In (SI) Hold Time 50 ns (min) t 7 Data In (SI) Set-Up Time to SC (Clock) High 30 ns (min) 10090904 FIGURE 2. Data Output Timing Diagram www.national.com 5 |
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