![]() |
Electronic Components Datasheet Search |
|
LM78CCVF-J Datasheet(PDF) 7 Page - National Semiconductor (TI) |
|
|
LM78CCVF-J Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 31 page ![]() AC Electrical Characteristics(Note 13) The following specifications apply for +4.25 V DC ≤ VCC ≤ +5.75 V DC unless otherwise specified. Boldface limits apply for TA =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. Symbol Parameter Conditions Typical Limits Units (Note 8) (Note 9) (Limits) ISA TIMING CHARACTERISTICS f SYSCLK System Clock (SYSCLK) Input Frequency 8.33 MHz t CS(setup) CS Active to IORD/IOWR Active 10 ns (min) t CS (hold) IORD/IOWR Inactive to CS Inactive 10 ns (min) t SA(setup) Address Valid to IORD/IOWR Active 30 ns (min) t SA (hold) IORD/IOWR Inactive to Address Invalid 10 ns (min) ISA WRITE TIMING t SDWR(setup) Data Valid to IOWR Active 5 ns (min) t SDWR (hold) IOWR Inactive to Data Invalid 5 ns (min) t WR(setup) IOWR Active to Rising Edge of SYSCLK 20 ns (min) DS012873-4 The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that an Power-on reset does not occur unintentionally. (See Section 3.2 ‘Resets’ ) FIGURE 1. ISA Bus Write Timing Diagram www.national.com 7 |
Similar Part No. - LM78CCVF-J |
|
Similar Description - LM78CCVF-J |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |
allmanual.com |