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LM78CCVF-J Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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LM78CCVF-J Datasheet(HTML) 8 Page - National Semiconductor (TI) |
8 / 31 page ![]() AC Electrical Characteristics(Note 13) The following specifications apply for +4.25 V DC ≤ VCC ≤ +5.75 VDC unless otherwise specified. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. (Continued) Symbol Parameter Conditions Typical Limits Units (Note 8) (Note 9) (Limits) ISA READ TIMING t SDRD (setup) Data Valid to IORD Inactive 120 ns (min) t SDRD (hold) IORD Inactive to Data Invalid 5 ns (min) t RD(setup) IORD Active to Rising Edge of SYSCLK 20 ns (min) t RS (delay) Rising Edge of SYSCLK number 1 to Data Valid With 8.33 MHz SYSCLK 360 ns (max) DS012873-5 The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that an Power-on reset does not occur unintentionally. (SeeSection 3.2‘Resets’ ) FIGURE 2. ISA Bus Read Timing Diagram www.national.com 8 |
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