Rev 1, 04/21/2016

Latched Parallel Mode:

Latched Parallel Mode is selected when V

Latched Parallel Mode:

•

•

Set LE to logic low.

•

Adjust pins [26, 27, 28, 29, 30, 31, 32] to the desired attenuation setting.

low, the attenuation state will not change.

•

Pull LE to a logic high. The device will then transition to the attenuation settings reflected by pins

D6 - D0.

Latched Parallel Default Startup Condition:

Latched Parallel Mode implies a default state for when the device is first powered up with V

low and LE logic low. In this case the default setting is MAXIMUM Attenuation.

Table 4 - Truth Table for the Parallel Control Word

D6

D5

D4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

1

1

Figure 5 -

9

7-Bit, 75

Adjust pins [26, 27, 28, 29, 30, 31, 32] to the desired attenuation setting. (W

low, the attenuation state will not change.)

The device will then transition to the attenuation settings reflected by pins

Latched Parallel Default Startup Condition:

Latched Parallel Mode implies a default state for when the device is first powered up with V

. In this case the default setting is MAXIMUM Attenuation.

Truth Table for the Parallel Control Word

D3

D2

D1

D0

Attenuation

(dB)

0

0

0

0

0

0

0

1

0

0

1

0

0

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

31.75

- Latched Parallel Mode Timing Diagram

F1977

75 Ω

Ω

Ω

Ω, Digital Step Attenuator

logic low to high. To utilize

While LE is set to a logic

The device will then transition to the attenuation settings reflected by pins

Attenuation

(dB)

0

0.25

0.5

1

2

4

8

16

31.75