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F1956 Datasheet(PDF) 10 Page - Integrated Device Technology |
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F1956 Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 23 page F1956 7-Bit 0.25 dB Wideband Digital Step Attenuator 10 Rev 2 04/08/2016 Table 5 - Latched Parallel Mode Timing Interval Symbol Description Min Spec Max Spec Units tsps Serial to Parallel Mode Setup Time 100 ns tpdh Parallel Data Hold Time 10 ns tle LE minimum pulse width 10 ns tpds Parallel Data Setup Time 10 ns TYPICAL OPERATING CONDITIONS (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply. 1. VDD = +3.30 V 2. TCASE = +25 °C 3. 50 MHz Tone Space 4. Serial Control 5. PIN = 0 dBm 6. RF1 is the input port 7. Attenuation Setting = 0 dB 8. EVKit losses (traces and connectors) are fully de-embedded |
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