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X3101PT-V Datasheet(PDF) 9 Page - Xicor Inc. |
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X3101PT-V Datasheet(HTML) 9 Page - Xicor Inc. |
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9 / 40 page  X3100/X3101 – Preliminary Information Characteristics subject to change without notice. 9 of 40 REV 1.1.8 12/10/02 www.xicor.com Table 8. Cell Charging Threshold Voltage Selection. Cell Number Selection The X3100 is designed to operate with four (4) Li-Ion battery cells. The X3101 is designed to operate with three (3) Li-Ion battery cells. The CELLN bit of the configuration register (Table 9) sets the number of cells recognized. For the X3101, the value for CELLN should always be zero. Table 9. Selection of Number of Battery Cells1 The configuration register consists of 16 bits of NOVRAM memory (Table 2, Table 3). This memory features a high-speed static RAM (SRAM) overlaid bit- for-bit with non-volatile “Shadow” EEPROM. An automatic array recall operation reloads the contents of the shadow EEPROM into the SRAM configuration register upon power-up (Figure 3). Figure 3. Power up of Configuration Register The configuration register is designed for unlimited write operations to SRAM, and a minimum of 1,000,000 store operations to the EEPROM. Data retention is specified to be greater than 100 years. It should be noted that the bits of the shadow EEPROM are for the dedicated use of the configuration register, and are NOT part of the general purpose 4kbit EEPROM array. T he WCFIG command writes to the configuration register, see Table 30 and section “X3100/X3101 SPI Serial Communication” on page 22. After writing to this register using a WCFIG instruction, data will be stored only in the SRAM of the configuration register. In order to store data in shadow EEPROM, a WREN instruction, followed by a EEWRITE to any address of the 4kbit EEPROM memory array must occur, see Figure 4. This sequence initiates an internal nonvolatile write cycle which permits data to be stored in the shadow EEPROM cells. It must be noted that even though a EEWRITE is made to the general purpose 4kbit EEPROM array, the value and address to which it is written, is unimportant. If this procedure is not followed, the configuration register will power up to the last previously stored values following a power down sequence. Configuration Register Bits Operation VCE1 VCE0 00 VCE = 0.5V 01 VCE = 0.80V 10 VCE = 1.10V 11 VCE = 1.40V Configuration Register Bit Operation CELLN 1 4 Li-Ion battery cells (X3100 default) 0 3 Li-Ion battery cells (X3100 or X3101) 1. In the case that the X3100 or X3101 is configured for use with only three Li-Ion battery cells (i.e. CELLN=0), then VCELL4 (pin 7) MUST be tied to Vss (pin 9) to ensure correct operation. Configuration Register (SRAM) Shadow EEPROM Recall Recall Upper Byte Lower Byte |
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