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TMS5700432BPZQQ1R Datasheet(PDF) 6 Page - Texas Instruments |
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TMS5700432BPZQQ1R Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 110 page  TMS570LS0432, TMS570LS0332 SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 www.ti.com Table of Contents 1 Device Overview ......................................... 1 6.9 Flash Memory ....................................... 50 6.10 Flash Program and Erase Timings for Program 1.1 Features .............................................. 1 Flash ................................................ 52 1.2 Applications ........................................... 2 6.11 Flash Program and Erase Timings for Data Flash .. 52 1.3 Description ............................................ 3 6.12 Tightly Coupled RAM Interface Module ............. 53 1.4 Functional Block Diagram ............................ 5 6.13 Parity Protection for Accesses to peripheral RAMs . 53 2 Revision History ......................................... 7 6.14 On-Chip SRAM Initialization and Testing ........... 54 3 Device Comparison ..................................... 8 6.15 Vectored Interrupt Manager ......................... 56 4 Terminal Configuration and Functions ............. 9 6.16 Real-Time Interrupt Module ......................... 58 4.1 PZ QFP Package Pinout (100-Pin) ................... 9 6.17 Error Signaling Module .............................. 59 4.2 Terminal Functions ................................. 10 6.18 Reset / Abort / Error Sources ....................... 63 4.3 Output Multiplexing and Control ..................... 16 6.19 Digital Windowed Watchdog ........................ 64 4.4 Special Multiplexed Options ......................... 17 6.20 Debug Subsystem ................................... 65 5 Specifications .......................................... 18 7 Peripheral Information and Electrical 5.1 Absolute Maximum Ratings ......................... 18 Specifications ........................................... 70 5.2 ESD Ratings ........................................ 18 7.1 Peripheral Legend ................................... 70 5.3 Power-On Hours (POH) ............................. 18 7.2 Multibuffered 12-Bit Analog-to-Digital Converter .... 70 5.4 Recommended Operating Conditions ............... 19 7.3 General-Purpose Input/Output ...................... 78 5.5 Switching Characteristics Over Recommended 7.4 Enhanced High-End Timer (N2HET) ................ 79 Operating Conditions for Clock Domains ........... 19 7.5 Controller Area Network (DCAN) .................... 82 5.6 Wait States Required ............................... 20 7.6 Local Interconnect Network Interface (LIN) ......... 83 5.7 Power Consumption ................................ 21 7.7 Multibuffered / Standard Serial Peripheral Interface 84 5.8 Thermal Resistance Characteristics for PZ ......... 22 7.8 Enhanced Quadrature Encoder (eQEP) ............ 94 5.9 Input/Output Electrical Characteristics .............. 22 8 Device and Documentation Support ............... 96 5.10 Output Buffer Drive Strengths ...................... 23 8.1 Device Support ...................................... 96 5.11 Input Timings ........................................ 24 8.2 Documentation Support ............................. 99 5.12 Output Timings ...................................... 25 8.3 Related Links ........................................ 99 6 System Information and Electrical Specifications ........................................... 27 8.4 Community Resources .............................. 99 6.1 Voltage Monitor Characteristics ..................... 27 8.5 Trademarks .......................................... 99 6.2 Power Sequencing and Power-On Reset ........... 28 8.6 Electrostatic Discharge Caution ..................... 99 6.3 Warm Reset (nRST) ................................. 30 8.7 Glossary ............................................. 99 6.4 ARM Cortex-R4 CPU Information ................... 31 8.8 Device Identification Code Register ............... 100 6.5 Clocks ............................................... 35 8.9 Die Identification Registers ....................... 100 6.6 Clock Monitoring .................................... 41 8.10 Module Certifications ............................... 101 6.7 Glitch Filters ......................................... 43 9 Mechanical Packaging and Orderable Addendum .............................................. 106 6.8 Device Memory Map ................................ 44 9.1 Packaging Information ............................. 106 6 Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332 |
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