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X9251TV24-2.7 Datasheet(PDF) 1 Page - Xicor Inc. |
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X9251TV24-2.7 Datasheet(HTML) 1 Page - Xicor Inc. |
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1 / 25 page  REV 1.3.3 2/10/04 Characteristics subject to change without notice. 1 of 25 www.xicor.com X9251 Quad Digitally-Controlled (XDCPTM) Potentiometer FEATURES • Four potentiometers in one package • 256 resistor taps–0.4% resolution • SPI Serial Interface for write, read, and transfer operations of the potentiometer • Wiper resistance: 100 Ω typical @ VCC = 5V •4 Non-volatile data registers for each potentiometer • Non-volatile storage of multiple wiper positions • Standby current < 5µA max •VCC: 2.7V to 5.5V Operation • 50K Ω, 100KΩ versions of total resistance • 100 yr. data retention • Single supply version of X9250 • Endurance: 100,000 data changes per bit per register • 24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip Scale Package) •Low power CMOS DESCRIPTION The X9251 integrates four digitally controlled potentio- meters (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are imple- mented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Single Supply / Low Power / 256-tap / SPI bus APPLICATION NOTES AND DEVELOPMENT SYSTEM A V A I L A B L E AN99 • AN115 • AN124 •AN133 • AN134 • AN135 FUNCTIONAL DIAGRAM POWER UP, INTERFACE CONTROL AND VCC VSS SPI RH0 RL0 DCP0 RW0 A1 SO SI CS HOLD SCK WP WCR0 DR00 DR01 DR02 DR03 RH1 RL1 DCP1 RW1 WCR1 DR10 DR11 DR12 DR13 RH2 RL2 DCP2 RW2 WCR2 DR20 DR21 DR22 DR23 RH3 RL3 DCP3 RW3 WCR3 DR30 DR31 DR32 DR33 A0 Interface STATUS |
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