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X9258UV24-2.7 Datasheet(PDF) 2 Page - Xicor Inc.

Part # X9258UV24-2.7
Description  Quad Digital Controlled Potentiometers (XDCP)
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Manufacturer  XICOR [Xicor Inc.]
Direct Link  http://www.xicor.com
Logo XICOR - Xicor Inc.

X9258UV24-2.7 Datasheet(HTML) 2 Page - Xicor Inc.

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X9258
Characteristics subject to change without notice.
2 of 22
REV 1.1.7 2/4/03
www.xicor.com
PIN DESCRIPTIONS
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the
X9258.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
DEVICE ADDRESS (A0–A3)
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with
the
address
input
in
order
to
initiate
communication with the X9258. A maximum of 16
devices may occupy the 2-wire serial bus.
Potentiometer Pins
VH/RH (VH0/RH0–VH3/RH3), VL/RL (VL0/RL0–VL3/RL3)
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
VW/RW (VW0/RW0–VW3/RW3)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages
for the DCP analog section.
PIN CONFIGURATION
NC
A0
VW3/RW3
V+
VCC
VL0/RL0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
A3
SCL
VL2/RL2
VH2/RH2
VW2/RW2
V–
VSS
VW1/RW1
VH1/RH1
VL1/RL1
SOIC/TSSOP
X9258
VH3/RH3
14
13
11
12
VL3/RL3
VH0/RH0
VW0/RW0
A2
A1
SDA
WP
2
3
4
A
B
C
D
E
F
Top View–Bumps Down
RW0
RL0
V+
A0
A3
RL1
VCC
RL3
RW3
NC
SDA
RW1
SCL
RL2
WP
V-
RH0
RH1
RH3
VSS
RW2
A2
A1
1
CSP
RH2


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