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X9251TV24I-2.7 Datasheet(PDF) 4 Page - Xicor Inc.

Part # X9251TV24I-2.7
Description  Quad Digitally-Controlled (XDCP) Potentiometer
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Manufacturer  XICOR [Xicor Inc.]
Direct Link  http://www.xicor.com
Logo XICOR - Xicor Inc.

X9251TV24I-2.7 Datasheet(HTML) 4 Page - Xicor Inc.

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X9251
Characteristics subject to change without notice.
4 of 25
REV 1.3.3 2/10/04
www.xicor.com
PIN CONFIGURATION
PIN ASSIGNMENTS
Note 1: A0–A1 device address pins must be tied to a logic level.
Pin
(SOIC)
Pin
(CSP)
Symbol
Function
1E2SO
Serial Data Output for SPI bus
2F2A0
Device Address for SPI bus. (See Note 1)
3F1
RW3
Wiper Terminal of DCP3
4D2
RH3
High Terminal of DCP3
5E1
RL3
Low Terminal of DCP3
7C1
VCC
System Supply Voltage
8B1
RL0
Low Terminal of DCP0
9C2
RH0
High Terminal of DCP0
10
A1
RW0
Wiper Terminal of DCP0
11
A2
CS
SPI bus. Chip Select active low input
12
B2
WP
Hardware Write Protect – active low
13
B3
SI
Serial Data Input for SPI bus
14
A3
A1
Device Address for SPI bus. (See Note 1)
15
A4
RL1
Low Terminal of DCP1
16
C3
RH1
High Terminal of DCP1
17
B4
RW1
Wiper Terminal of DCP1
18
C4
VSS
System Ground
20
E4
RW2
Wiper Terminal of DCP2
21
D3
RH2
High Terminal of DCP2
22
F4
RL2
Low Terminal of DCP2
23
F3
SCK
Serial Clock for SPI bus
24
E3
HOLD
Device select. Pauses the SPI serial bus.
6, 19
D1, D4
NC
No Connect
2
3
4
A
B
C
D
E
F
Top View–Bumps Down
RW0
RL0
NC
A0
HOLD
RL1
VCC
RL3
RW3
SO
SI
RW1
SCK
RL2
WP
NC
RH0
RH1
RH3
VSS
RW2
CS
A1
1
CSP
RH2
SO
A0
RW3
NC
VCC
RL0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
RL2
RH2
RW2
NC
VSS
RW1
RH1
RL1
SOIC/TSSOP
X9251
RH3
14
13
11
12
RL3
RH0
RW0
CS
A1
SI
WP


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