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IS82C37A-5 Datasheet(PDF) 5 Page - Harris Corporation |
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IS82C37A-5 Datasheet(HTML) 5 Page - Harris Corporation |
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5 / 23 page  4-196 82C37A Functional Description The 82C37A direct memory access controller is designed to improve the data transfer rate in systems which must transfer data from an I/O device to memory, or move a block of memory to an I/O device. It will also perform memory-to- memory block moves, or fill a block of memory with data from a single location. Operating modes are provided to handle single byte transfers as well as discontinuous data streams, which allows the 82C37A to control data movement with software transparency. The DMA controller is a state-driven address and control signal generator, which permits data to be transferred directly from an I/O device to memory or vice versa without ever being stored in a temporary register. This can greatly increase the data transfer rate for sequential operations, compared with processor move or repeated string instructions. Memory-to-memory operations require temporary internal storage of the data byte between generation of the source and destination addresses, so memory-to-memory transfers take place at less than half the rate of I/O operations, but still much faster than with central processor techniques. The maximum data transfer rates obtainable with the 82C37A are shown in Figure 1. The block diagram of the 82C37A is shown on page 2. The timing and control block, priority block, and internal registers are the main components. Figure 2 lists the name and size of the internal registers. The timing and control block derives internal timing from clock input, and generates external control signals. The Priority Encoder block resolves priority contention between DMA channels requesting service simultaneously. DMA Operation In a system, the 82C37A address and control outputs and data bus pins are basically connected in parallel with the system busses. An external latch is required for the upper address byte. While inactive, the controller’s outputs are in a high impedance state. When activated by a DMA request and bus control is relinquished by the host, the 82C37A drives the busses and generates the control signals to perform the data transfer. The operation performed by activating one of the four DMA request inputs has previously been programmed into the controller via the Command, Mode, Address, and Word Count registers. For example, if a block of data is to be transferred from RAM to an I/O device, the starting address of the data is loaded into the 82C37A Current and Base Address registers for a particular channel, and the length of the block is loaded into the channel’s Word Count register. The corresponding Mode register is programmed for a memory-to-I/O operation (read transfer), and various options are selected by the Command register and the other Mode register bits. The channel’s mask bit is cleared to enable recognition of a DMA request (DREQ). The DREQ can either be a hardware signal or a software command. Once initiated, the block DMA transfer will proceed as the controller outputs the data address, simultaneous MEMR and IOW pulses, and selects an I/O device via the DMA acknowledge (DACK) outputs. The data byte flows directly from the RAM to the I/O device. After each byte is transferred, the address is automatically incremented (or decremented) and the word count is decremented. The operation is then repeated for the next byte. The controller stops transferring data when the Word Count register underflows, or an external EOP is applied. To further understand 82C37A operation, the states generated by each clock cycle must be considered. The DMA controller operates in two major cycles, active and idle. After being programmed, the controller is normally idle until a DMA request occurs on an unmasked channel, or a software request is given. The 82C37A will then request control of the system busses and enter the active cycle. The active cycle is composed of several internal states, depending on what options have been selected and what type of operation has been requested. 82C37A TRANSFER TYPE 5MHz 8MHz 12.5MHz UNIT Compressed 2.50 4.00 6.25 MByte/sec Normal I/O 1.67 2.67 4.17 MByte/sec Memory-to- Memory 0.63 1.00 1.56 MByte/sec FIGURE 1. DMA TRANSFER RATES NAME SIZE NUMBER Base Address Registers 16-Bits 4 Base Word Count Registers 16-Bits 4 Current Address Registers 16-Bits 4 Current Word Count Registers 16-Bits 4 Temporary Address Register 16-Bits 1 Temporary Word Count Register 16-Bits 1 Status Register 8-Bits 1 Command Register 8-Bits 1 Temporary Register 8-Bits 1 Mode Registers 6-Bits 4 Mask Register 4-Bits 1 Request Register 4-Bits 1 FIGURE 2. 82C37A INTERNAL REGISTERS |
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